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drivers: ethernet: xlnx_gem: update referenced SoC configuration items

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Update the Kconfig configuration items used to determine if the current
target is based on the Zynq-7000 SoC family as part of the re-organi-
zation of the Zynq-7000 SoC configuration data.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
This commit is contained in:
Immo Birnbaum 2021-11-11 14:19:37 +01:00 • committed by Anas Nashif
commit 99a6598b98
3 changed files with 8 additions and 8 deletions
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2
drivers/ethernet/Kconfig.xlnx_gem
View file

@ -11,7 +11,7 @@ DT_COMPAT_XLNX_GEM := xlnx,gem
menuconfig ETH_XLNX_GEM menuconfig ETH_XLNX_GEM
bool "Xilinx GEM Ethernet driver" bool "Xilinx GEM Ethernet driver"
default $(dt_compat_enabled,$(DT_COMPAT_XLNX_GEM)) default $(dt_compat_enabled,$(DT_COMPAT_XLNX_GEM))
depends on SOC_XILINX_ZYNQMP_RPU || SOC_SERIES_XILINX_ZYNQ7000 depends on SOC_XILINX_ZYNQMP_RPU || SOC_FAMILY_XILINX_ZYNQ7000
depends on !QEMU_TARGET || (QEMU_TARGET && NET_QEMU_ETHERNET) depends on !QEMU_TARGET || (QEMU_TARGET && NET_QEMU_ETHERNET)
help help
Enable Xilinx GEM Ethernet driver. Enable Xilinx GEM Ethernet driver.

6
drivers/ethernet/eth_xlnx_gem.c
View file

@ -120,7 +120,7 @@ static int eth_xlnx_gem_dev_init(const struct device *dev)
"%s invalid MDC clock divider value %u, must be in " "%s invalid MDC clock divider value %u, must be in "
"range 0 to %u", dev->name, dev_conf->mdc_divider, "range 0 to %u", dev->name, dev_conf->mdc_divider,
(uint32_t)MDC_DIVIDER_48); (uint32_t)MDC_DIVIDER_48);
#elif defined(CONFIG_SOC_SERIES_XILINX_ZYNQ7000) #elif defined(CONFIG_SOC_FAMILY_XILINX_ZYNQ7000)
__ASSERT(dev_conf->mdc_divider <= MDC_DIVIDER_224, __ASSERT(dev_conf->mdc_divider <= MDC_DIVIDER_224,
"%s invalid MDC clock divider value %u, must be in " "%s invalid MDC clock divider value %u, must be in "
"range 0 to %u", dev->name, dev_conf->mdc_divider, "range 0 to %u", dev->name, dev_conf->mdc_divider,
@ -818,7 +818,7 @@ static void eth_xlnx_gem_configure_clocks(const struct device *dev)
if ((tmp & ETH_XLNX_CRL_APB_WPROT_BIT) > 0) { if ((tmp & ETH_XLNX_CRL_APB_WPROT_BIT) > 0) {
sys_write32(tmp, ETH_XLNX_CRL_APB_WPROT_REGISTER_ADDRESS); sys_write32(tmp, ETH_XLNX_CRL_APB_WPROT_REGISTER_ADDRESS);
} }
# elif defined(CONFIG_SOC_SERIES_XILINX_ZYNQ7000) # elif defined(CONFIG_SOC_FAMILY_XILINX_ZYNQ7000)
clk_ctrl_reg = sys_read32(dev_conf->clk_ctrl_reg_address); clk_ctrl_reg = sys_read32(dev_conf->clk_ctrl_reg_address);
clk_ctrl_reg &= ~((ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK << clk_ctrl_reg &= ~((ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK <<
ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR0_SHIFT) | ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR0_SHIFT) |
@ -838,7 +838,7 @@ static void eth_xlnx_gem_configure_clocks(const struct device *dev)
sys_write32(clk_ctrl_reg, dev_conf->clk_ctrl_reg_address); sys_write32(clk_ctrl_reg, dev_conf->clk_ctrl_reg_address);
sys_write32(ETH_XLNX_SLCR_LOCK_KEY, sys_write32(ETH_XLNX_SLCR_LOCK_KEY,
ETH_XLNX_SLCR_LOCK_REGISTER_ADDRESS); ETH_XLNX_SLCR_LOCK_REGISTER_ADDRESS);
#endif /* CONFIG_SOC_XILINX_ZYNQMP / CONFIG_SOC_SERIES_XILINX_ZYNQ7000 */ #endif /* CONFIG_SOC_XILINX_ZYNQMP / CONFIG_SOC_FAMILY_XILINX_ZYNQ7000 */
LOG_DBG("%s set clock dividers div0/1 %u/%u for target " LOG_DBG("%s set clock dividers div0/1 %u/%u for target "
"frequency %u Hz", dev->name, div0, div1, target); "frequency %u Hz", dev->name, div0, div1, target);

8
drivers/ethernet/eth_xlnx_gem_priv.h
View file

@ -110,7 +110,7 @@
#define ETH_XLNX_GEM_CKSUM_NOT_TCP_OR_UDP_ERROR 0x00000006 #define ETH_XLNX_GEM_CKSUM_NOT_TCP_OR_UDP_ERROR 0x00000006
#define ETH_XLNX_GEM_CKSUM_PREMATURE_END_ERROR 0x00000007 #define ETH_XLNX_GEM_CKSUM_PREMATURE_END_ERROR 0x00000007
#if defined(CONFIG_SOC_SERIES_XILINX_ZYNQ7000) #if defined(CONFIG_SOC_FAMILY_XILINX_ZYNQ7000)
/* /*
* Zynq-7000 TX clock configuration: * Zynq-7000 TX clock configuration:
* *
@ -152,7 +152,7 @@
#define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR0_SHIFT 8 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR0_SHIFT 8
#define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_RX_CLKACT_BIT 0x04000000 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_RX_CLKACT_BIT 0x04000000
#define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_CLKACT_BIT 0x02000000 #define ETH_XLNX_CRL_APB_GEMX_REF_CTRL_CLKACT_BIT 0x02000000
#endif /* CONFIG_SOC_SERIES_XILINX_ZYNQ7000 || CONFIG_SOC_XILINX_ZYNQMP */ #endif /* CONFIG_SOC_FAMILY_XILINX_ZYNQ7000 || CONFIG_SOC_XILINX_ZYNQMP */
/* /*
* Register offsets within the respective GEM's address space: * Register offsets within the respective GEM's address space:
@ -512,7 +512,7 @@ struct eth_xlnx_dma_area_gem##port {\
}; };
/* DMA memory area instantiation macro */ /* DMA memory area instantiation macro */
#ifdef CONFIG_SOC_SERIES_XILINX_ZYNQ7000 #ifdef CONFIG_SOC_FAMILY_XILINX_ZYNQ7000
#define ETH_XLNX_GEM_DMA_AREA_INST(port) \ #define ETH_XLNX_GEM_DMA_AREA_INST(port) \
static struct eth_xlnx_dma_area_gem##port eth_xlnx_gem##port##_dma_area\ static struct eth_xlnx_dma_area_gem##port eth_xlnx_gem##port##_dma_area\
__ocm_bss_section __aligned(4096); __ocm_bss_section __aligned(4096);
@ -597,7 +597,7 @@ enum eth_xlnx_mdc_clock_divider {
MDC_DIVIDER_16, MDC_DIVIDER_16,
MDC_DIVIDER_32, MDC_DIVIDER_32,
MDC_DIVIDER_48, MDC_DIVIDER_48,
#ifdef CONFIG_SOC_SERIES_XILINX_ZYNQ7000 #ifdef CONFIG_SOC_FAMILY_XILINX_ZYNQ7000
/* Dividers > 48 are only available in the Zynq-7000 */ /* Dividers > 48 are only available in the Zynq-7000 */
MDC_DIVIDER_64, MDC_DIVIDER_64,
MDC_DIVIDER_96, MDC_DIVIDER_96,