michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: ethernet: xlnx_gem: update referenced SoC configuration items

Browse source 
Update the Kconfig configuration items used to determine if the current
target is based on the Zynq-7000 SoC family as part of the re-organi-
zation of the Zynq-7000 SoC configuration data.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
This commit is contained in:
Immo Birnbaum 2021-11-11 14:19:37 +01:00 • committed by Anas Nashif
commit 99a6598b98
3 changed files with 8 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

6
drivers/ethernet/eth_xlnx_gem.c
View file

@ -120,7 +120,7 @@ static int eth_xlnx_gem_dev_init(const struct device *dev)
"%s invalid MDC clock divider value %u, must be in "
"range 0 to %u", dev->name, dev_conf->mdc_divider,
(uint32_t)MDC_DIVIDER_48);
#elif defined(CONFIG_SOC_SERIES_XILINX_ZYNQ7000)
#elif defined(CONFIG_SOC_FAMILY_XILINX_ZYNQ7000)
__ASSERT(dev_conf->mdc_divider <= MDC_DIVIDER_224,
"%s invalid MDC clock divider value %u, must be in "
"range 0 to %u", dev->name, dev_conf->mdc_divider,
@ -818,7 +818,7 @@ static void eth_xlnx_gem_configure_clocks(const struct device *dev)
if ((tmp & ETH_XLNX_CRL_APB_WPROT_BIT) > 0) {
sys_write32(tmp, ETH_XLNX_CRL_APB_WPROT_REGISTER_ADDRESS);
}
# elif defined(CONFIG_SOC_SERIES_XILINX_ZYNQ7000)
# elif defined(CONFIG_SOC_FAMILY_XILINX_ZYNQ7000)
clk_ctrl_reg = sys_read32(dev_conf->clk_ctrl_reg_address);
clk_ctrl_reg &= ~((ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK <<
ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR0_SHIFT) |
@ -838,7 +838,7 @@ static void eth_xlnx_gem_configure_clocks(const struct device *dev)
sys_write32(clk_ctrl_reg, dev_conf->clk_ctrl_reg_address);
sys_write32(ETH_XLNX_SLCR_LOCK_KEY,
ETH_XLNX_SLCR_LOCK_REGISTER_ADDRESS);
#endif /* CONFIG_SOC_XILINX_ZYNQMP / CONFIG_SOC_SERIES_XILINX_ZYNQ7000 */
#endif /* CONFIG_SOC_XILINX_ZYNQMP / CONFIG_SOC_FAMILY_XILINX_ZYNQ7000 */
LOG_DBG("%s set clock dividers div0/1 %u/%u for target "
"frequency %u Hz", dev->name, div0, div1, target);