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llext: add support for arc

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Adds compiler flag(s) and some architecture-specific relocations
for ARC. No userspace support, doesn't support all relocations.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
This commit is contained in:
Lauren Murphy 2024-09-11 14:26:22 -07:00 • committed by Anas Nashif
commit 99a5236b40
8 changed files with 137 additions and 11 deletions
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6
tests/subsys/llext/simple/boards/qemu_arc_qemu_arc_em.conf Normal file
View file

@ -0,0 +1,6 @@
CONFIG_FILE_SYSTEM=y
CONFIG_FILE_SYSTEM_LITTLEFS=y
CONFIG_FS_LITTLEFS_FMP_DEV=y
CONFIG_FLASH_MAP=y
CONFIG_FLASH=y
CONFIG_FLASH_SIMULATOR=y

28
tests/subsys/llext/simple/boards/qemu_arc_qemu_arc_em.overlay Normal file
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@ -0,0 +1,28 @@
/ {
sim_flash_controller: sim_flash_controller {
compatible = "zephyr,sim-flash";
#address-cells = <1>;
#size-cells = <1>;
erase-value = <0x00>;
flash_sim0: flash_sim@0 {
compatible = "soc-nv-flash";
reg = <0x00000000 0x2000>;
erase-block-size = <1024>;
write-block-size = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage_partition";
reg = <0x00000000 0x2000>;
};
};
};
};
};

1
tests/subsys/llext/simple/no_mem_protection.conf
View file

@ -6,3 +6,4 @@
CONFIG_ARM_MPU=n
CONFIG_ARM_AARCH32_MMU=n
CONFIG_RISCV_PMP=n
CONFIG_ARC_MPU_ENABLE=n

19
tests/subsys/llext/simple/testcase.yaml
View file

@ -6,11 +6,6 @@ common:
- s32z2xxdc2/s32z270/rtu0 # See commit 18a0660
- s32z2xxdc2/s32z270/rtu1 # See commit 18a0660
# platforms that are always skipped by the runtime filter
- qemu_arc/qemu_arc_em
- qemu_arc/qemu_arc_hs
- qemu_arc/qemu_arc_hs/xip
- qemu_arc/qemu_arc_hs5x
- qemu_arc/qemu_arc_hs6x
- qemu_cortex_m0
- qemu_xtensa/dc233c/mmu
integration_platforms:
@ -36,7 +31,7 @@ tests:
# most tests include no_mem_protection.conf, which disables memory protection
# hardware completely.
llext.simple.readonly:
arch_allow: arm riscv # Xtensa needs writable storage
arch_allow: arm riscv arc # Xtensa needs writable storage
filter: not CONFIG_MPU and not CONFIG_MMU
extra_conf_files: ['no_mem_protection.conf']
extra_configs:
@ -57,7 +52,7 @@ tests:
- CONFIG_LLEXT_HEAP_SIZE=128 # qemu_cortex_a9 requires larger heap
- CONFIG_LLEXT_STORAGE_WRITABLE=n
llext.simple.writable:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
@ -65,7 +60,9 @@ tests:
extra_configs:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
llext.simple.writable_relocatable:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
platform_exclude:
- qemu_arc/qemu_arc_hs5x # See #80949
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
@ -77,7 +74,7 @@ tests:
# Test the Symbol Link Identifier (SLID) linking feature on writable
# storage to cover both ARM and Xtensa architectures on the same test.
llext.simple.writable_slid_linking:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
@ -86,7 +83,9 @@ tests:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
- CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID=y
llext.simple.writable_relocatable_slid_linking:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
platform_exclude:
- qemu_arc/qemu_arc_hs5x # See #80949
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU