diff --git a/soc/riscv/riscv-ite/common/CMakeLists.txt b/soc/riscv/riscv-ite/common/CMakeLists.txt
index 7191c35da80..857950b4c7f 100644
--- a/soc/riscv/riscv-ite/common/CMakeLists.txt
+++ b/soc/riscv/riscv-ite/common/CMakeLists.txt
@@ -1,6 +1,7 @@
 zephyr_include_directories(.)
 
 zephyr_sources(
+  check_regs.c
   soc_irq.S
   soc_common_irq.c
   vector.S
diff --git a/soc/riscv/riscv-ite/common/check_regs.c b/soc/riscv/riscv-ite/common/check_regs.c
new file mode 100644
index 00000000000..fc2500f02f7
--- /dev/null
+++ b/soc/riscv/riscv-ite/common/check_regs.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <soc.h>
+
+/* GCTRL register structure check */
+IT8XXX2_REG_SIZE_CHECK(gctrl_it8xxx2_regs, 0x88);
+IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RSTS, 0x06);
+IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_SPCTRL4, 0x1c);
+IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RSTC5, 0x21);
+IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_MCCR2, 0x44);
+IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_ECHIPID2, 0x86);
diff --git a/soc/riscv/riscv-ite/common/chip_chipregs.h b/soc/riscv/riscv-ite/common/chip_chipregs.h
index 0f7271fe597..9d1f372e55b 100644
--- a/soc/riscv/riscv-ite/common/chip_chipregs.h
+++ b/soc/riscv/riscv-ite/common/chip_chipregs.h
@@ -734,6 +734,17 @@
 #define CLS			BIT(1)
 #define DLS			BIT(0)
 
+/*
+ * IT8XXX2 register structure size/offset checking macro function to mitigate
+ * the risk of unexpected compiling results.
+ */
+#define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \
+	BUILD_ASSERT(sizeof(struct reg_def) == size, \
+		"Failed in size check of register structure!")
+#define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \
+	BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
+		"Failed in offset check of register structure member!")
+
 /**
  *
  * (18xxh) PWM & SmartAuto Fan Control (PWM)