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dts/st: dtc v1.4.6 warnings: pin-c... node has a reg ... no unit name

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To prepare to upcoming dtc v1.4.6, fix warnings in dts files.

This commit addresses the following warning:
Warning (unit_address_vs_reg): Node /soc/pin-controller has a reg
or ranges property, but no unit name

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2018-04-24 15:32:10 +02:00 • committed by Kumar Gala
commit 986f249f03
25 changed files with 25 additions and 25 deletions
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2
dts/arm/st/stm32f0-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
usart1_pins_a: usart1@0 { usart1_pins_a: usart1@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUPDR_NO_PULL)>; rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUPDR_NO_PULL)>;

2
dts/arm/st/stm32f0.dtsi
View file

@ -56,7 +56,7 @@
label = "STM32_CLK_RCC"; label = "STM32_CLK_RCC";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
compatible = "st,stm32-pinmux"; compatible = "st,stm32-pinmux";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

2
dts/arm/st/stm32f072.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 { gpioe: gpio@48001000 {
compatible = "st,stm32-gpio"; compatible = "st,stm32-gpio";

2
dts/arm/st/stm32f091.dtsi
View file

@ -18,7 +18,7 @@
label = "SPI_2"; label = "SPI_2";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 { gpioe: gpio@48001000 {
compatible = "st,stm32-gpio"; compatible = "st,stm32-gpio";

2
dts/arm/st/stm32f1-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40010800 {
usart1_pins_a: usart1@0 { usart1_pins_a: usart1@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PA10 STM32_PIN_USART_RX>; rx = <STM32_PIN_PA10 STM32_PIN_USART_RX>;

2
dts/arm/st/stm32f1.dtsi
View file

@ -44,7 +44,7 @@
label = "STM32_CLK_RCC"; label = "STM32_CLK_RCC";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@40010800 {
compatible = "st,stm32-pinmux"; compatible = "st,stm32-pinmux";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

2
dts/arm/st/stm32f103Xe.dtsi
View file

@ -20,7 +20,7 @@
status = "disabled"; status = "disabled";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@40010800 {
reg = <0x40010800 0x2000>; reg = <0x40010800 0x2000>;
gpiof: gpio@40011c00 { gpiof: gpio@40011c00 {

2
dts/arm/st/stm32f3-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
usart1_pins_a: usart1@0 { usart1_pins_a: usart1@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>; rx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;

2
dts/arm/st/stm32f3.dtsi
View file

@ -54,7 +54,7 @@
label = "STM32_CLK_RCC"; label = "STM32_CLK_RCC";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
compatible = "st,stm32-pinmux"; compatible = "st,stm32-pinmux";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

2
dts/arm/st/stm32f303.dtsi
View file

@ -35,7 +35,7 @@
label = "SPI_2"; label = "SPI_2";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 { gpioe: gpio@48001000 {
compatible = "st,stm32-gpio"; compatible = "st,stm32-gpio";

2
dts/arm/st/stm32f4-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
usart1_pins_a: usart1@0 { usart1_pins_a: usart1@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>; rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;

2
dts/arm/st/stm32f4.dtsi
View file

@ -56,7 +56,7 @@
label = "STM32_CLK_RCC"; label = "STM32_CLK_RCC";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
compatible = "st,stm32-pinmux"; compatible = "st,stm32-pinmux";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

2
dts/arm/st/stm32f405-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
usart3_pins_a: usart3@0 { usart3_pins_a: usart3@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>; rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;

2
dts/arm/st/stm32f405.dtsi
View file

@ -14,7 +14,7 @@
}; };
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2400>; reg = <0x40020000 0x2400>;
gpiof: gpio@40021400 { gpiof: gpio@40021400 {

2
dts/arm/st/stm32f412-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
usart3_pins_a: usart3@0 { usart3_pins_a: usart3@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>; rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;

2
dts/arm/st/stm32f412.dtsi
View file

@ -9,7 +9,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x1c00>; reg = <0x40020000 0x1c00>;
gpiof: gpio@40021400 { gpiof: gpio@40021400 {

2
dts/arm/st/stm32f413-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
usart3_pins_a: usart3@0 { usart3_pins_a: usart3@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>; rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;

2
dts/arm/st/stm32f429.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2C00>; reg = <0x40020000 0x2C00>;
gpioj: gpio@40022400 { gpioj: gpio@40022400 {

2
dts/arm/st/stm32l0-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@50000000 {
usart1_pins_a: usart1@0 { usart1_pins_a: usart1@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUPDR_NO_PULL)>; rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUPDR_NO_PULL)>;

2
dts/arm/st/stm32l0.dtsi
View file

@ -56,7 +56,7 @@
label = "STM32_CLK_RCC"; label = "STM32_CLK_RCC";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@50000000 {
compatible = "st,stm32-pinmux"; compatible = "st,stm32-pinmux";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

2
dts/arm/st/stm32l072.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@50000000 {
gpioe: gpio@50001000 { gpioe: gpio@50001000 {
compatible = "st,stm32-gpio"; compatible = "st,stm32-gpio";

2
dts/arm/st/stm32l4-pinctrl.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
usart1_pins_a: usart1@0 { usart1_pins_a: usart1@0 {
rx_tx { rx_tx {
rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>; rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;

2
dts/arm/st/stm32l4.dtsi
View file

@ -57,7 +57,7 @@
label = "STM32_CLK_RCC"; label = "STM32_CLK_RCC";
}; };
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
compatible = "st,stm32-pinmux"; compatible = "st,stm32-pinmux";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

2
dts/arm/st/stm32l475.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
gpiod: gpio@48000c00 { gpiod: gpio@48000c00 {
compatible = "st,stm32-gpio"; compatible = "st,stm32-gpio";

2
dts/arm/st/stm32l496.dtsi
View file

@ -8,7 +8,7 @@
/ { / {
soc { soc {
pinctrl: pin-controller { pinctrl: pin-controller@48000000 {
reg = <0x48000000 0x2400>; reg = <0x48000000 0x2400>;
gpioi: gpio@480002000 { gpioi: gpio@480002000 {