dts: mipi_dsi: introduce phy-clock property

Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.

Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.

Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts

@@ -74,7 +74,11 @@
 	dpi-bllp-mode = "low-power";
 	autoinsert-eotp;
 	dphy-ref-frequency = <24000000>;
-
+	/*
+	 * PHY clock is given by the following formula:
+	 * (pixel clock * bits per pixel) / MIPI data lanes
+	 */
+	phy-clock = <748154880>;
 	rm68200@0 {
 		status = "okay";
 		compatible = "raydium,rm68200";

boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts

@@ -178,7 +178,11 @@
 	dpi-video-mode = "burst";
 	dpi-bllp-mode = "low-power";
 	autoinsert-eotp;
-	dphy-clk-div = <12>;
+	/*
+	 * PHY clock is given by the following formula:
+	 * (pixel clock * bits per pixel) / MIPI data lanes
+	 */
+	phy-clock = <748154880>;
 
 	rm68200@0 {
 		status = "okay";

drivers/mipi_dsi/dsi_mcux.c

@@ -32,6 +32,7 @@ struct display_mcux_mipi_dsi_config {
 	MIPI_DSI_Type base;
 	dsi_dpi_config_t dpi_config;
 	bool auto_insert_eotp;
+	uint32_t phy_clock;
 };
 
 struct display_mcux_mipi_dsi_data {
@@ -69,7 +70,7 @@ static int dsi_mcux_attach(const struct device *dev,
 	 * Note that the DSI output pixel is 24bit per pixel.
 	 */
 	uint32_t mipi_dsi_dpi_clk_hz = CLOCK_GetRootClockFreq(kCLOCK_Root_Lcdif);
-	uint32_t mipi_dsi_dphy_bit_clk_hz = mipi_dsi_dpi_clk_hz * (24 / mdev->data_lanes);
+	uint32_t mipi_dsi_dphy_bit_clk_hz = config->phy_clock;
 
 	mipi_dsi_dphy_bit_clk_hz = MIPI_DPHY_BIT_CLK_ENLARGE(mipi_dsi_dphy_bit_clk_hz);
 
@@ -195,6 +196,7 @@ static int display_mcux_mipi_dsi_init(const struct device *dev)
 			.vbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vbp),			\
 		},										\
 		.auto_insert_eotp = DT_INST_PROP(id, autoinsert_eotp),				\
+		.phy_clock = DT_INST_PROP(id, phy_clock),					\
 	};											\
 	static struct display_mcux_mipi_dsi_data display_mcux_mipi_dsi_data_##id;		\
 	DEVICE_DT_INST_DEFINE(id,								\

dts/bindings/mipi-dsi/mipi-dsi-host.yaml

@@ -15,3 +15,9 @@ properties:
   "#size-cells":
     required: true
     const: 0
+
+  phy-clock:
+    type: int
+    description:
+      MIPI PHY clock frequency. Should be set to ensure clock frequency is at
+      least (pixel clock * bits per output pixel) / number of mipi data lanes

dts/bindings/mipi-dsi/nxp,mipi-dsi-2l.yaml

@@ -64,13 +64,6 @@ properties:
     description:
       Automatically insert an EoTp short packet when switching from HS to LP mode.
 
-  dphy-clk-div:
-    type: int
-    required: true
-    description:
-      MIPI D-PHY clock divider. Must be set to ensure clock frequency is at
-      least (pixel clock * bits per output pixel) / number of mipi data lanes
-
   dphy-ref-frequency:
     type: int
     default: 0

soc/arm/nxp_imx/rt5xx/soc.c

@@ -422,12 +422,13 @@ void imxrt_pre_init_display_interface(void)
 	 *     (Pixel clock * bit per output pixel) / number of MIPI data lane
 	 *
 	 * DPHY supports up to 895.1MHz bit clock.
-	 * Note: AUX1 PLL clock is system pll clock * 18 / pfd.
+	 * We set the divider of the PFD3 output of the SYSPLL, which has a
-	 * system pll clock is configured at 528MHz by default.
+	 * fixed multiplied of 18, and use this output frequency for the DPHY.
 	 */
 	CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK);
 	CLOCK_InitSysPfd(kCLOCK_Pfd3,
-		DT_PROP(DT_NODELABEL(mipi_dsi), dphy_clk_div));
+		((CLOCK_GetSysPllFreq() * 18ull) /
+		((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock)))));
 	CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1);
 
 	/* Clear DSI control reset (Note that DPHY reset is cleared later)*/