diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ec5a7e4526a..cdb5ec7d93c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -90,12 +90,6 @@ config RISCV_SOC_INTERRUPT_INIT
 	  Enable SOC-based interrupt initialization
 	  (call soc_interrupt_init, within _IntLibInit when enabled)
 
-config RISCV_SOC_INIT_GP_VALUE
-	bool "Enable SOC-based global pointer register initialization"
-	help
-	  Enable SOC-based pointer register initialization
-	  (call __soc_get_gp_initial_value when initializing a thread)
-
 config RISCV_GENERIC_TOOLCHAIN
 	bool "Compile using generic riscv32 toolchain"
 	default y
diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c
index cc066f27f90..9ad30a4b223 100644
--- a/arch/riscv/core/thread.c
+++ b/arch/riscv/core/thread.c
@@ -47,10 +47,6 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	stack_init->a2 = (ulong_t)p2;
 	stack_init->a3 = (ulong_t)p3;
 
-#ifdef CONFIG_RISCV_SOC_INIT_GP_VALUE
-	stack_init->gp = __soc_get_gp_initial_value();
-#endif
-
 #ifdef CONFIG_THREAD_LOCAL_STORAGE
 	stack_init->tp = (ulong_t)thread->tls;
 #endif
diff --git a/soc/riscv/esp32c3/soc.c b/soc/riscv/esp32c3/soc.c
index e53e823d91f..96245fbe283 100644
--- a/soc/riscv/esp32c3/soc.c
+++ b/soc/riscv/esp32c3/soc.c
@@ -186,9 +186,3 @@ int arch_irq_is_enabled(unsigned int irq)
 {
 	return (REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG) & (1 << irq));
 }
-
-ulong_t __soc_get_gp_initial_value(void)
-{
-	extern uint32_t __global_pointer$;
-	return (ulong_t)&__global_pointer$;
-}
diff --git a/soc/riscv/esp32c3/soc.h b/soc/riscv/esp32c3/soc.h
index 85cbca3e63f..8218d8ebf0c 100644
--- a/soc/riscv/esp32c3/soc.h
+++ b/soc/riscv/esp32c3/soc.h
@@ -41,8 +41,6 @@ extern STATUS esp_rom_uart_tx_one_char(uint8_t chr);
 extern STATUS esp_rom_uart_rx_one_char(uint8_t *chr);
 extern void esp_rom_ets_set_user_start(uint32_t start);
 
-ulong_t __soc_get_gp_initial_value(void);
-
 #endif /* _ASMLANGUAGE */
 
 #endif /* __SOC_H__ */