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arm: rename instances of CortexM

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Directory names: CortexM -> cortex_m
Code comments: CortexM -> Cortex-M

Change-Id: If946ed25fac863e0be9dbb6f6c275199402b0b0a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This commit is contained in:
Benjamin Walsh 2015-08-20 16:46:11 -04:00 • committed by Anas Nashif
commit 97f2622f55
23 changed files with 34 additions and 34 deletions
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2
arch/arm/core/cortex_m/Kconfig
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@ -1,4 +1,4 @@
# Kconfig - ARM CortexM platform configuration options
# Kconfig - ARM Cortex-M platform configuration options
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.

6
arch/arm/include/asm_inline.h
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@ -34,13 +34,13 @@
#define _ASM_INLINE_H
#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEX_M)
#error arch/arm/include/asm_inline.h is for ARM CortexM only
#error arch/arm/include/asm_inline.h is for ARM Cortex-M only
#endif
#if defined(__GNUC__)
#include <CortexM/asm_inline_gcc.h>
#include <cortex_m/asm_inline_gcc.h>
#else
#include <CortexM/asm_inline_other.h>
#include <cortex_m/asm_inline_other.h>
#endif /* __GNUC__ */
#endif /* _ASM_INLINE_H */

2
arch/arm/include/CortexM/asm_inline_gcc.h → arch/arm/include/cortex_m/asm_inline_gcc.h
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@ -1,4 +1,4 @@
/* ARM CortexM GCC specific inline assembler functions and macros */
/* ARM Cortex-M GCC specific inline assembler functions and macros */
/*
* Copyright (c) 2015, Wind River Systems, Inc.

0
arch/arm/include/CortexM/exc.h → arch/arm/include/cortex_m/exc.h
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0
arch/arm/include/CortexM/stack.h → arch/arm/include/cortex_m/stack.h
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4
arch/arm/include/nano_private.h
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@ -121,8 +121,8 @@ typedef struct preempt tPreempt;
#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
#ifdef CONFIG_CPU_CORTEX_M
#include <CortexM/stack.h>
#include <CortexM/exc.h>
#include <cortex_m/stack.h>
#include <cortex_m/exc.h>
#endif
#ifndef _ASMLANGUAGE

2
arch/arm/platforms/fsl_frdm_k64f/linker.cmd
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@ -43,4 +43,4 @@ This is the linker script for both standard images and XIP images.
*/
#define SKIP_TO_SECURITY_FRDM_K64F . = 0x400;
#include <arch/arm/CortexM/scripts/linker.cmd>
#include <arch/arm/cortex_m/scripts/linker.cmd>

2
arch/arm/platforms/ti_lm3s6965/linker.cmd
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@ -30,4 +30,4 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/arm/CortexM/scripts/linker.cmd>
#include <arch/arm/cortex_m/scripts/linker.cmd>

2
include/arch/arc/v2/misc.h
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@ -1,4 +1,4 @@
/* CortexM/misc.h - Cortex-M public nanokernel miscellaneous */
/* arc/v2/misc.h - ARCv2 public nanokernel miscellaneous */
/*
* Copyright (c) 2014 Wind River Systems, Inc.

20
include/arch/arm/arch.h
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@ -50,16 +50,16 @@ extern "C" {
#define SIZEOFUNIT_TO_OCTET(X) (X)
#ifdef CONFIG_CPU_CORTEX_M
#include <arch/arm/CortexM/exc.h>
#include <arch/arm/CortexM/irq.h>
#include <arch/arm/CortexM/error.h>
#include <arch/arm/CortexM/misc.h>
#include <arch/arm/CortexM/scs.h>
#include <arch/arm/CortexM/scb.h>
#include <arch/arm/CortexM/nvic.h>
#include <arch/arm/CortexM/memory_map.h>
#include <arch/arm/CortexM/gdb_stub.h>
#include <arch/arm/CortexM/asm_inline.h>
#include <arch/arm/cortex_m/exc.h>
#include <arch/arm/cortex_m/irq.h>
#include <arch/arm/cortex_m/error.h>
#include <arch/arm/cortex_m/misc.h>
#include <arch/arm/cortex_m/scs.h>
#include <arch/arm/cortex_m/scb.h>
#include <arch/arm/cortex_m/nvic.h>
#include <arch/arm/cortex_m/memory_map.h>
#include <arch/arm/cortex_m/gdb_stub.h>
#include <arch/arm/cortex_m/asm_inline.h>
#endif
#define STACK_ALIGN 4

4
include/arch/arm/CortexM/asm_inline.h → include/arch/arm/cortex_m/asm_inline.h
View file

@ -39,9 +39,9 @@
*/
#if defined(__GNUC__)
#include <arch/arm/CortexM/asm_inline_gcc.h>
#include <arch/arm/cortex_m/asm_inline_gcc.h>
#else
#include <arch/arm/CortexM/asm_inline_other.h>
#include <arch/arm/cortex_m/asm_inline_other.h>
#endif
#endif /* _ASM_INLINE_PUBLIC_H */

4
include/arch/arm/CortexM/asm_inline_gcc.h → include/arch/arm/cortex_m/asm_inline_gcc.h
View file

@ -1,4 +1,4 @@
/* Intel ARM GCC specific public inline assembler functions and macros */
/* ARM Cortex-M GCC specific public inline assembler functions and macros */
/*
* Copyright (c) 2015, Wind River Systems, Inc.
@ -50,7 +50,7 @@
#else /* !_ASMLANGUAGE */
#include <stdint.h>
#include <arch/arm/CortexM/nvic.h>
#include <arch/arm/cortex_m/nvic.h>
/**
*

4
include/arch/arm/CortexM/error.h → include/arch/arm/cortex_m/error.h
View file

@ -1,4 +1,4 @@
/* CortexM/error.h - Cortex-M public error handling */
/* cortex_m/error.h - Cortex-M public error handling */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
@ -38,7 +38,7 @@ ARM-specific nanokernel error handling interface. Included by ARM/arch.h.
#ifndef _ARCH_ARM_CORTEXM_ERROR_H_
#define _ARCH_ARM_CORTEXM_ERROR_H_
#include <arch/arm/CortexM/exc.h>
#include <arch/arm/cortex_m/exc.h>
#ifndef _ASMLANGUAGE
extern FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int,

2
include/arch/arm/CortexM/exc.h → include/arch/arm/cortex_m/exc.h
View file

@ -1,4 +1,4 @@
/* CortexM/exc.h - Cortex-M public exception handling */
/* cortex_m/exc.h - Cortex-M public exception handling */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.

0
include/arch/arm/CortexM/gdb_stub.h → include/arch/arm/cortex_m/gdb_stub.h
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4
include/arch/arm/CortexM/irq.h → include/arch/arm/cortex_m/irq.h
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@ -1,4 +1,4 @@
/* CortexM/irq.h - Cortex-M public interrupt handling */
/* cortex_m/irq.h - Cortex-M public interrupt handling */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
@ -38,7 +38,7 @@ ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h.
#ifndef _ARCH_ARM_CORTEXM_IRQ_H_
#define _ARCH_ARM_CORTEXM_IRQ_H_
#include <arch/arm/CortexM/nvic.h>
#include <arch/arm/cortex_m/nvic.h>
#include <sw_isr_table.h>
#ifdef _ASMLANGUAGE

0
include/arch/arm/CortexM/memory_map-m3-m4.h → include/arch/arm/cortex_m/memory_map-m3-m4.h
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2
include/arch/arm/CortexM/memory_map.h → include/arch/arm/cortex_m/memory_map.h
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@ -73,7 +73,7 @@ processors.
/* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
#if defined(CONFIG_CPU_CORTEX_M3_M4)
#include <arch/arm/CortexM/memory_map-m3-m4.h>
#include <arch/arm/cortex_m/memory_map-m3-m4.h>
#else
#error Unknown CPU
#endif

2
include/arch/arm/CortexM/misc.h → include/arch/arm/cortex_m/misc.h
View file

@ -1,4 +1,4 @@
/* CortexM/misc.h - Cortex-M public nanokernel miscellaneous */
/* cortex_m/misc.h - Cortex-M public nanokernel miscellaneous */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.

2
include/arch/arm/CortexM/nvic.h → include/arch/arm/cortex_m/nvic.h
View file

@ -51,7 +51,7 @@ Supports up to 240 IRQs and 256 priority levels.
#ifndef _NVIC_H_
#define _NVIC_H_
#include <arch/arm/CortexM/scs.h>
#include <arch/arm/cortex_m/scs.h>
/* for assembler, only works with constants */
#define _EXC_PRIO(pri) (((pri) << (8 - CONFIG_NUM_IRQ_PRIO_BITS)) & 0xff)

2
include/arch/arm/CortexM/scb.h → include/arch/arm/cortex_m/scb.h
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@ -66,7 +66,7 @@ registers is the way to implement it.
#include <nanokernel.h>
#include <arch/cpu.h>
#include <misc/__assert.h>
#include <arch/arm/CortexM/scs.h>
#include <arch/arm/cortex_m/scs.h>
#include <misc/util.h>
#include <stdint.h>

0
include/arch/arm/CortexM/scripts/linker.cmd → include/arch/arm/cortex_m/scripts/linker.cmd
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2
include/arch/arm/CortexM/scs.h → include/arch/arm/cortex_m/scs.h
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@ -73,7 +73,7 @@ still considered part of the NVIC and an API for it is provided in nvic.h.
#ifdef _ASMLANGUAGE
#include <arch/arm/CortexM/memory_map.h>
#include <arch/arm/cortex_m/memory_map.h>
#else /* _ASMLANGUAGE */