drivers: memc: Add NXP FlexRAM driver
Add driver for NXP FlexRAM Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
parent
71b0db2118
commit
97d991f7d6
5 changed files with 366 additions and 2 deletions
|
@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c)
|
|||
zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_W956A8MBYA memc_mcux_flexspi_w956a8mbya.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_S27KS0641 memc_mcux_flexspi_s27ks0641.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6408L memc_mcux_flexspi_aps6408l.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_MEMC_NXP_FLEXRAM memc_nxp_flexram.c)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_MEMC_SAM_SMC memc_sam_smc.c)
|
||||
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2020-2022 NXP
|
||||
# Copyright 2020-2023 NXP
|
||||
# Copyright (c) 2021 Basalte bv
|
||||
# Copyright (c) 2023, ithinx GmbH
|
||||
# Copyright (c) 2023, Tonies GmbH
|
||||
|
@ -28,4 +28,23 @@ config MEMC_MCUX_FLEXSPI
|
|||
bool
|
||||
select PINCTRL
|
||||
|
||||
endif
|
||||
endif # DT_HAS_NXP_IMX_FLEXSPI_ENABLED
|
||||
|
||||
|
||||
if DT_HAS_NXP_FLEXRAM_ENABLED
|
||||
|
||||
config MEMC_NXP_FLEXRAM
|
||||
bool
|
||||
default y
|
||||
|
||||
config MEMC_NXP_FLEXRAM_MAGIC_ADDR_API
|
||||
bool "NXP FlexRAM magic addr API"
|
||||
help
|
||||
Enable API to use flexRAM magic address functionality
|
||||
|
||||
config MEMC_NXP_FLEXRAM_ERROR_INTERRUPT
|
||||
bool "NXP FlexRAM error interrupt"
|
||||
help
|
||||
Allow flexram to generate error interrupts
|
||||
|
||||
endif # DT_HAS_NXP_FLEXRAM_ENABLED
|
||||
|
|
231
drivers/memc/memc_nxp_flexram.c
Normal file
231
drivers/memc/memc_nxp_flexram.c
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "memc_nxp_flexram.h"
|
||||
#include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <errno.h>
|
||||
#include <zephyr/irq.h>
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
|
||||
#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
|
||||
BUILD_ASSERT(DT_PROP(FLEXRAM_DT_NODE, flexram_has_magic_addr),
|
||||
"SOC does not support magic flexram addresses");
|
||||
#endif
|
||||
|
||||
#define BANK_SIZE (DT_PROP(FLEXRAM_DT_NODE, flexram_bank_size) * 1024)
|
||||
#define NUM_BANKS DT_PROP(FLEXRAM_DT_NODE, flexram_num_ram_banks)
|
||||
|
||||
#define IS_CHILD_RAM_TYPE(node_id, compat) DT_NODE_HAS_COMPAT(node_id, compat)
|
||||
#define DOES_RAM_TYPE_EXIST(compat) \
|
||||
DT_FOREACH_CHILD_SEP_VARGS(FLEXRAM_DT_NODE, IS_CHILD_RAM_TYPE, (+), compat)
|
||||
|
||||
#if DOES_RAM_TYPE_EXIST(mmio_sram)
|
||||
#define FIND_OCRAM_NODE(node_id) \
|
||||
COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, mmio_sram), (node_id), ())
|
||||
#define OCRAM_DT_NODE DT_FOREACH_CHILD(FLEXRAM_DT_NODE, FIND_OCRAM_NODE)
|
||||
#define OCRAM_START (DT_REG_ADDR(OCRAM_DT_NODE))
|
||||
#define OCRAM_END (OCRAM_START + DT_REG_SIZE(OCRAM_DT_NODE))
|
||||
#endif /* OCRAM */
|
||||
#if DOES_RAM_TYPE_EXIST(nxp_imx_dtcm)
|
||||
#define FIND_DTCM_NODE(node_id) \
|
||||
COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nxp_imx_dtcm), (node_id), ())
|
||||
#define DTCM_DT_NODE DT_FOREACH_CHILD(FLEXRAM_DT_NODE, FIND_DTCM_NODE)
|
||||
#define DTCM_START (DT_REG_ADDR(DTCM_DT_NODE))
|
||||
#define DTCM_END (DTCM_START + DT_REG_SIZE(DTCM_DT_NODE))
|
||||
#endif /* DTCM */
|
||||
#if DOES_RAM_TYPE_EXIST(nxp_imx_itcm)
|
||||
#define FIND_ITCM_NODE(node_id) \
|
||||
COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nxp_imx_itcm), (node_id), ())
|
||||
#define ITCM_DT_NODE DT_FOREACH_CHILD(FLEXRAM_DT_NODE, FIND_ITCM_NODE)
|
||||
#define ITCM_START (DT_REG_ADDR(ITCM_DT_NODE))
|
||||
#define ITCM_END (ITCM_START + DT_REG_SIZE(ITCM_DT_NODE))
|
||||
#endif /* ITCM */
|
||||
|
||||
|
||||
#ifdef FLEXRAM_RUNTIME_BANKS_USED
|
||||
|
||||
#define PLUS_ONE_BANK(node_id, prop, idx) 1
|
||||
#define COUNT_BANKS \
|
||||
DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, PLUS_ONE_BANK, (+))
|
||||
BUILD_ASSERT(COUNT_BANKS == NUM_BANKS, "wrong number of flexram banks defined");
|
||||
|
||||
#ifdef OCRAM_DT_NODE
|
||||
#define ADD_BANK_IF_OCRAM(node_id, prop, idx) \
|
||||
COND_CODE_1(IS_EQ(DT_PROP_BY_IDX(node_id, prop, idx), FLEXRAM_OCRAM), \
|
||||
(BANK_SIZE), (0))
|
||||
#define OCRAM_TOTAL \
|
||||
DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, ADD_BANK_IF_OCRAM, (+))
|
||||
BUILD_ASSERT((OCRAM_TOTAL) == DT_REG_SIZE(OCRAM_DT_NODE), "OCRAM node size is wrong");
|
||||
#endif /* OCRAM */
|
||||
|
||||
#ifdef DTCM_DT_NODE
|
||||
#define ADD_BANK_IF_DTCM(node_id, prop, idx) \
|
||||
COND_CODE_1(IS_EQ(DT_PROP_BY_IDX(node_id, prop, idx), FLEXRAM_DTCM), \
|
||||
(BANK_SIZE), (0))
|
||||
#define DTCM_TOTAL \
|
||||
DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, ADD_BANK_IF_DTCM, (+))
|
||||
BUILD_ASSERT((DTCM_TOTAL) == DT_REG_SIZE(DTCM_DT_NODE), "DTCM node size is wrong");
|
||||
#endif /* DTCM */
|
||||
|
||||
#ifdef ITCM_DT_NODE
|
||||
#define ADD_BANK_IF_ITCM(node_id, prop, idx) \
|
||||
COND_CODE_1(IS_EQ(DT_PROP_BY_IDX(node_id, prop, idx), FLEXRAM_ITCM), \
|
||||
(BANK_SIZE), (0))
|
||||
#define ITCM_TOTAL \
|
||||
DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, ADD_BANK_IF_ITCM, (+))
|
||||
BUILD_ASSERT((ITCM_TOTAL) == DT_REG_SIZE(ITCM_DT_NODE), "ITCM node size is wrong");
|
||||
#endif /* ITCM */
|
||||
|
||||
#endif /* FLEXRAM_RUNTIME_BANKS_USED */
|
||||
|
||||
static FLEXRAM_Type *const base = (FLEXRAM_Type *) DT_REG_ADDR(FLEXRAM_DT_NODE);
|
||||
|
||||
#ifdef FLEXRAM_INTERRUPTS_USED
|
||||
static flexram_callback_t flexram_callback;
|
||||
static void *flexram_user_data;
|
||||
|
||||
void memc_flexram_register_callback(flexram_callback_t callback, void *user_data)
|
||||
{
|
||||
flexram_callback = callback;
|
||||
flexram_user_data = user_data;
|
||||
}
|
||||
|
||||
static void nxp_flexram_isr(void *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
if (flexram_callback == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT)
|
||||
if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) {
|
||||
base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK;
|
||||
flexram_callback(flexram_ocram_access_error, flexram_user_data);
|
||||
}
|
||||
if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) {
|
||||
base->INT_STATUS |= FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK;
|
||||
flexram_callback(flexram_dtcm_access_error, flexram_user_data);
|
||||
}
|
||||
if (base->INT_STATUS & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) {
|
||||
base->INT_STATUS |= FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK;
|
||||
flexram_callback(flexram_itcm_access_error, flexram_user_data);
|
||||
}
|
||||
#endif /* CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT */
|
||||
|
||||
#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
|
||||
if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) {
|
||||
base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK;
|
||||
flexram_callback(flexram_ocram_magic_addr, flexram_user_data);
|
||||
}
|
||||
if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) {
|
||||
base->INT_STATUS |= FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK;
|
||||
flexram_callback(flexram_dtcm_magic_addr, flexram_user_data);
|
||||
}
|
||||
if (base->INT_STATUS & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) {
|
||||
base->INT_STATUS |= FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK;
|
||||
flexram_callback(flexram_itcm_magic_addr, flexram_user_data);
|
||||
}
|
||||
#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
|
||||
int memc_flexram_set_ocram_magic_addr(uint32_t ocram_addr)
|
||||
{
|
||||
#ifdef OCRAM_DT_NODE
|
||||
ocram_addr -= DT_REG_ADDR(OCRAM_DT_NODE);
|
||||
if (ocram_addr >= DT_REG_SIZE(OCRAM_DT_NODE)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
base->OCRAM_MAGIC_ADDR &= ~FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK;
|
||||
base->OCRAM_MAGIC_ADDR |= FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(ocram_addr);
|
||||
|
||||
base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK;
|
||||
return 0;
|
||||
#else
|
||||
return -ENODEV;
|
||||
#endif
|
||||
}
|
||||
|
||||
int memc_flexram_set_itcm_magic_addr(uint32_t itcm_addr)
|
||||
{
|
||||
#ifdef ITCM_DT_NODE
|
||||
itcm_addr -= DT_REG_ADDR(ITCM_DT_NODE);
|
||||
if (itcm_addr >= DT_REG_SIZE(ITCM_DT_NODE)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
base->ITCM_MAGIC_ADDR &= ~FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK;
|
||||
base->ITCM_MAGIC_ADDR |= FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(itcm_addr);
|
||||
|
||||
base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK;
|
||||
return 0;
|
||||
#else
|
||||
return -ENODEV;
|
||||
#endif
|
||||
}
|
||||
|
||||
int memc_flexram_set_dtcm_magic_addr(uint32_t dtcm_addr)
|
||||
{
|
||||
#ifdef DTCM_DT_NODE
|
||||
dtcm_addr -= DT_REG_ADDR(DTCM_DT_NODE);
|
||||
if (dtcm_addr >= DT_REG_SIZE(DTCM_DT_NODE)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
base->DTCM_MAGIC_ADDR &= ~FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK;
|
||||
base->DTCM_MAGIC_ADDR |= FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(dtcm_addr);
|
||||
|
||||
base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK;
|
||||
return 0;
|
||||
#else
|
||||
return -ENODEV;
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
|
||||
|
||||
#endif /* FLEXRAM_INTERRUPTS_USED */
|
||||
|
||||
static int nxp_flexram_init(void)
|
||||
{
|
||||
if (DT_PROP(FLEXRAM_DT_NODE, flexram_tcm_read_wait_mode)) {
|
||||
base->TCM_CTRL |= FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;
|
||||
}
|
||||
if (DT_PROP(FLEXRAM_DT_NODE, flexram_tcm_write_wait_mode)) {
|
||||
base->TCM_CTRL |= FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT)
|
||||
base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK;
|
||||
base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK;
|
||||
base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK;
|
||||
base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK;
|
||||
base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK;
|
||||
base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK;
|
||||
#endif /* CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT */
|
||||
|
||||
#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
|
||||
base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK;
|
||||
base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK;
|
||||
base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK;
|
||||
#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
|
||||
|
||||
#ifdef FLEXRAM_INTERRUPTS_USED
|
||||
IRQ_CONNECT(DT_IRQN(FLEXRAM_DT_NODE), DT_IRQ(FLEXRAM_DT_NODE, priority),
|
||||
nxp_flexram_isr, NULL, 0);
|
||||
irq_enable(DT_IRQN(FLEXRAM_DT_NODE));
|
||||
#endif /* FLEXRAM_INTERRUPTS_USED */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(nxp_flexram_init, EARLY, 0);
|
98
drivers/memc/memc_nxp_flexram.h
Normal file
98
drivers/memc/memc_nxp_flexram.h
Normal file
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <soc.h>
|
||||
|
||||
#define FLEXRAM_DT_NODE DT_INST(0, nxp_flexram)
|
||||
#define IOMUXC_GPR_DT_NODE DT_INST(0, nxp_imx_gpr)
|
||||
|
||||
#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API) || \
|
||||
defined(CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT)
|
||||
#define FLEXRAM_INTERRUPTS_USED
|
||||
#endif
|
||||
|
||||
#if DT_PROP_HAS_IDX(FLEXRAM_DT_NODE, flexram_bank_spec, 0)
|
||||
#define FLEXRAM_RUNTIME_BANKS_USED 1
|
||||
#endif
|
||||
|
||||
#ifdef FLEXRAM_INTERRUPTS_USED
|
||||
enum memc_flexram_interrupt_cause {
|
||||
#ifdef CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT
|
||||
flexram_ocram_access_error,
|
||||
flexram_itcm_access_error,
|
||||
flexram_dtcm_access_error,
|
||||
#endif
|
||||
#ifdef CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API
|
||||
flexram_ocram_magic_addr,
|
||||
flexram_itcm_magic_addr,
|
||||
flexram_dtcm_magic_addr,
|
||||
#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
|
||||
};
|
||||
|
||||
typedef void (*flexram_callback_t)(enum memc_flexram_interrupt_cause, void *user_data);
|
||||
|
||||
void memc_flexram_register_callback(flexram_callback_t callback, void *user_data);
|
||||
#endif /* FLEXRAM_INTERRUPTS_USED */
|
||||
|
||||
#ifdef FLEXRAM_RUNTIME_BANKS_USED
|
||||
|
||||
/*
|
||||
* call from platform_init to set up flexram if using runtime map
|
||||
* must be inlined because cannot use stack
|
||||
*/
|
||||
#define GPR17_REG_FILL(node_id, prop, idx) + (DT_PROP_BY_IDX(node_id, prop, idx) << idx)
|
||||
static inline void memc_flexram_dt_partition(void)
|
||||
{
|
||||
/* iomuxc_gpr must be const (in ROM region) because used in reconfiguring ram */
|
||||
static IOMUXC_GPR_Type *const iomuxc_gpr =
|
||||
(IOMUXC_GPR_Type *) DT_REG_ADDR(IOMUXC_GPR_DT_NODE);
|
||||
/* do not create stack variables or use any data from ram in this function */
|
||||
iomuxc_gpr->GPR17 = DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE,
|
||||
flexram_bank_spec, GPR17_REG_FILL, (+));
|
||||
iomuxc_gpr->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
|
||||
}
|
||||
#endif /* FLEXRAM_RUNTIME_BANKS_USED */
|
||||
|
||||
|
||||
#ifdef CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API
|
||||
/** @brief Sets magic address for OCRAM
|
||||
*
|
||||
* Magic address allows core interrupt from FlexRAM when address
|
||||
* is accessed.
|
||||
*
|
||||
* @param ocram_addr: An address in OCRAM to set magic function on.
|
||||
* @retval 0 on success
|
||||
* @retval -EINVAL if ocram_addr is not in OCRAM
|
||||
* @retval -ENODEV if there is no OCRAM allocation in flexram
|
||||
*/
|
||||
int memc_flexram_set_ocram_magic_addr(uint32_t ocram_addr);
|
||||
|
||||
/** @brief Sets magic address for ITCM
|
||||
*
|
||||
* Magic address allows core interrupt from FlexRAM when address
|
||||
* is accessed.
|
||||
*
|
||||
* @param itcm_addr: An address in ITCM to set magic function on.
|
||||
* @retval 0 on success
|
||||
* @retval -EINVAL if itcm_addr is not in ITCM
|
||||
* @retval -ENODEV if there is no ITCM allocation in flexram
|
||||
*/
|
||||
int memc_flexram_set_itcm_magic_addr(uint32_t itcm_addr);
|
||||
|
||||
/** @brief Sets magic address for DTCM
|
||||
*
|
||||
* Magic address allows core interrupt from FlexRAM when address
|
||||
* is accessed.
|
||||
*
|
||||
* @param dtcm_addr: An address in DTCM to set magic function on.
|
||||
* @retval 0 on success
|
||||
* @retval -EINVAL if dtcm_addr is not in DTCM
|
||||
* @retval -ENODEV if there is no DTCM allocation in flexram
|
||||
*/
|
||||
int memc_flexram_set_dtcm_magic_addr(uint32_t dtcm_addr);
|
||||
|
||||
#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
|
15
include/zephyr/dt-bindings/memory-controller/nxp,flexram.h
Normal file
15
include/zephyr/dt-bindings/memory-controller/nxp,flexram.h
Normal file
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_NXP_FLEXRAM_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_NXP_FLEXRAM_H_
|
||||
|
||||
#define FLEXRAM_NONE 0
|
||||
#define FLEXRAM_OCRAM 1
|
||||
#define FLEXRAM_DTCM 2
|
||||
#define FLEXRAM_ITCM 3
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_NXP_FLEXRAM_H_ */
|
Loading…
Add table
Add a link
Reference in a new issue