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drivers: Rename reserved function names

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Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
This commit is contained in:
Patrik Flykt 2019-03-12 15:15:42 -06:00 • committed by Anas Nashif
commit 97b3bd11a7
110 changed files with 544 additions and 544 deletions
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2
arch/arm/core/cortex_m/nmi.c
View file

@ -73,7 +73,7 @@ void z_NmiInit(void)
* @return N/A
*/
void _NmiHandlerSet(void (*pHandler)(void))
void z_NmiHandlerSet(void (*pHandler)(void))
{
handler = pHandler;
}

6
arch/xtensa/core/xt_zephyr.S
View file

@ -11,7 +11,7 @@
.extern _interrupt_stack
.extern _kernel
#ifdef CONFIG_SYS_CLOCK_EXISTS
.extern _timer_int_handler
.extern timer_int_handler
#endif
.set _interrupt_stack_top, _interrupt_stack + CONFIG_ISR_STACK_SIZE
@ -279,7 +279,7 @@ _zxt_timer_int:
s32i a2, sp, 4
s32i a3, sp, 8
/* TODO: movi a2, _xt_interrupt_table */
movi a3, _timer_int_handler
movi a3, timer_int_handler
/* TODO: l32i a2, a2, 0 */
callx0 a3
/* Restore a2 and a3. */
@ -287,7 +287,7 @@ _zxt_timer_int:
l32i a3, sp, 8
#else
/* TODO: movi a6, _xt_interrupt_table */
movi a7, _timer_int_handler
movi a7, timer_int_handler
/* TODO: l32i a6, a6, 0 */
callx4 a7
#endif

6
drivers/adc/adc_context.h
View file

@ -61,16 +61,16 @@ struct adc_context {
#ifdef ADC_CONTEXT_USES_KERNEL_TIMER
#define ADC_CONTEXT_INIT_TIMER(_data, _ctx_name) \
._ctx_name.timer = _K_TIMER_INITIALIZER(_data._ctx_name.timer, \
._ctx_name.timer = Z_TIMER_INITIALIZER(_data._ctx_name.timer, \
adc_context_on_timer_expired, \
NULL)
#endif /* ADC_CONTEXT_USES_KERNEL_TIMER */
#define ADC_CONTEXT_INIT_LOCK(_data, _ctx_name) \
._ctx_name.lock = _K_SEM_INITIALIZER(_data._ctx_name.lock, 0, 1)
._ctx_name.lock = Z_SEM_INITIALIZER(_data._ctx_name.lock, 0, 1)
#define ADC_CONTEXT_INIT_SYNC(_data, _ctx_name) \
._ctx_name.sync = _K_SEM_INITIALIZER(_data._ctx_name.sync, 0, 1)
._ctx_name.sync = Z_SEM_INITIALIZER(_data._ctx_name.sync, 0, 1)
static inline void adc_context_request_next_sampling(struct adc_context *ctx)

8
drivers/bluetooth/hci/h4.c
View file

@ -60,7 +60,7 @@ static struct {
u8_t hdr[4];
};
} rx = {
.fifo = _K_FIFO_INITIALIZER(rx.fifo),
.fifo = Z_FIFO_INITIALIZER(rx.fifo),
};
static struct {
@ -68,7 +68,7 @@ static struct {
struct net_buf *buf;
struct k_fifo fifo;
} tx = {
.fifo = _K_FIFO_INITIALIZER(tx.fifo),
.fifo = Z_FIFO_INITIALIZER(tx.fifo),
};
static struct device *h4_dev;
@ -456,7 +456,7 @@ static const struct bt_hci_driver drv = {
.send = h4_send,
};
static int _bt_uart_init(struct device *unused)
static int bt_uart_init(struct device *unused)
{
ARG_UNUSED(unused);
@ -470,4 +470,4 @@ static int _bt_uart_init(struct device *unused)
return 0;
}
SYS_INIT(_bt_uart_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
SYS_INIT(bt_uart_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);

4
drivers/bluetooth/hci/h5.c
View file

@ -761,7 +761,7 @@ static const struct bt_hci_driver drv = {
.send = h5_queue,
};
static int _bt_uart_init(struct device *unused)
static int bt_uart_init(struct device *unused)
{
ARG_UNUSED(unused);
@ -776,4 +776,4 @@ static int _bt_uart_init(struct device *unused)
return 0;
}
SYS_INIT(_bt_uart_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
SYS_INIT(bt_uart_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);

4
drivers/bluetooth/hci/spi.c
View file

@ -529,7 +529,7 @@ static const struct bt_hci_driver drv = {
.send = bt_spi_send,
};
static int _bt_spi_init(struct device *unused)
static int bt_spi_init(struct device *unused)
{
ARG_UNUSED(unused);
@ -568,4 +568,4 @@ static int _bt_spi_init(struct device *unused)
return 0;
}
SYS_INIT(_bt_spi_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
SYS_INIT(bt_spi_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);

4
drivers/bluetooth/hci/userchan.c
View file

@ -213,7 +213,7 @@ static const struct bt_hci_driver drv = {
.send = uc_send,
};
static int _bt_uc_init(struct device *unused)
static int bt_uc_init(struct device *unused)
{
ARG_UNUSED(unused);
@ -222,7 +222,7 @@ static int _bt_uc_init(struct device *unused)
return 0;
}
SYS_INIT(_bt_uc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
SYS_INIT(bt_uc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
static void cmd_bt_dev_found(char *argv, int offset)
{

24
drivers/clock_control/nrf_power_clock.c
View file

@ -21,7 +21,7 @@ static u8_t m16src_ref;
static u8_t m16src_grd;
static u8_t k32src_initialized;
static int _m16src_start(struct device *dev, clock_control_subsys_t sub_system)
static int m16src_start(struct device *dev, clock_control_subsys_t sub_system)
{
bool blocking;
u32_t imask;
@ -103,7 +103,7 @@ hf_already_started:
}
}
static int _m16src_stop(struct device *dev, clock_control_subsys_t sub_system)
static int m16src_stop(struct device *dev, clock_control_subsys_t sub_system)
{
u32_t imask;
@ -144,7 +144,7 @@ static int _m16src_stop(struct device *dev, clock_control_subsys_t sub_system)
return 0;
}
static int _k32src_start(struct device *dev, clock_control_subsys_t sub_system)
static int k32src_start(struct device *dev, clock_control_subsys_t sub_system)
{
u32_t lf_clk_src;
u32_t imask;
@ -248,7 +248,7 @@ static int _k32src_start(struct device *dev, clock_control_subsys_t sub_system)
*/
nrf_clock_int_enable(NRF_CLOCK_INT_HF_STARTED_MASK);
err = _m16src_start(dev, false);
err = m16src_start(dev, false);
if (!err) {
NVIC_SetPendingIRQ(DT_NORDIC_NRF_CLOCK_0_IRQ_0);
} else {
@ -390,7 +390,7 @@ void nrf_power_clock_isr(void *arg)
NRF_CLOCK->EVENTS_DONE = 0;
/* Calibration done, stop 16M Xtal. */
err = _m16src_stop(dev, NULL);
err = m16src_stop(dev, NULL);
__ASSERT_NO_MSG(!err || err == -EBUSY);
/* Start timer for next calibration. */
@ -408,7 +408,7 @@ void nrf_power_clock_isr(void *arg)
*/
NRF_CLOCK->INTENSET = CLOCK_INTENSET_HFCLKSTARTED_Msk;
err = _m16src_start(dev, false);
err = m16src_start(dev, false);
if (!err) {
NVIC_SetPendingIRQ(DT_NORDIC_NRF_CLOCK_0_IRQ_0);
} else {
@ -435,7 +435,7 @@ void nrf_power_clock_isr(void *arg)
#endif
}
static int _clock_control_init(struct device *dev)
static int clock_control_init(struct device *dev)
{
/* TODO: Initialization will be called twice, once for 32KHz and then
* for 16 MHz clock. The vector is also shared for other power related
@ -453,26 +453,26 @@ static int _clock_control_init(struct device *dev)
}
static const struct clock_control_driver_api _m16src_clock_control_api = {
.on = _m16src_start,
.off = _m16src_stop,
.on = m16src_start,
.off = m16src_stop,
.get_rate = NULL,
};
DEVICE_AND_API_INIT(clock_nrf5_m16src,
DT_NORDIC_NRF_CLOCK_0_LABEL "_16M",
_clock_control_init, NULL, NULL, PRE_KERNEL_1,
clock_control_init, NULL, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&_m16src_clock_control_api);
static const struct clock_control_driver_api _k32src_clock_control_api = {
.on = _k32src_start,
.on = k32src_start,
.off = NULL,
.get_rate = NULL,
};
DEVICE_AND_API_INIT(clock_nrf5_k32src,
DT_NORDIC_NRF_CLOCK_0_LABEL "_32K",
_clock_control_init, NULL, NULL, PRE_KERNEL_1,
clock_control_init, NULL, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&_k32src_clock_control_api);

20
drivers/clock_control/stm32_ll_clock.c
View file

@ -14,22 +14,22 @@
#include "stm32_ll_clock.h"
/* Macros to fill up prescaler values */
#define _ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
#define ahb_prescaler(v) _ahb_prescaler(v)
#define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
#define ahb_prescaler(v) z_ahb_prescaler(v)
#define _apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
#define apb1_prescaler(v) _apb1_prescaler(v)
#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
#define apb1_prescaler(v) z_apb1_prescaler(v)
#ifndef CONFIG_SOC_SERIES_STM32F0X
#define _apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
#define apb2_prescaler(v) _apb2_prescaler(v)
#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
#define apb2_prescaler(v) z_apb2_prescaler(v)
#endif /* CONFIG_SOC_SERIES_STM32F0X */
#define _mco1_prescaler(v) LL_RCC_MCO1_DIV_ ## v
#define mco1_prescaler(v) _mco1_prescaler(v)
#define z_mco1_prescaler(v) LL_RCC_MCO1_DIV_ ## v
#define mco1_prescaler(v) z_mco1_prescaler(v)
#define _mco2_prescaler(v) LL_RCC_MCO2_DIV_ ## v
#define mco2_prescaler(v) _mco2_prescaler(v)
#define z_mco2_prescaler(v) LL_RCC_MCO2_DIV_ ## v
#define mco2_prescaler(v) z_mco2_prescaler(v)
/**
* @brief fill in AHB/APB buses configuration structure

8
drivers/clock_control/stm32f2x_ll_clock.c
View file

@ -17,11 +17,11 @@
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define _pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) _pllm(v)
#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) z_pllm(v)
#define _pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) _pllp(v)
#define z_pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) z_pllp(v)
/**
* @brief fill in pll configuration structure

8
drivers/clock_control/stm32f4x_ll_clock.c
View file

@ -17,11 +17,11 @@
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define _pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) _pllm(v)
#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) z_pllm(v)
#define _pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) _pllp(v)
#define z_pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) z_pllp(v)
/**
* @brief fill in pll configuration structure

8
drivers/clock_control/stm32f7x_ll_clock.c
View file

@ -15,11 +15,11 @@
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define _pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) _pllm(v)
#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) z_pllm(v)
#define _pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) _pllp(v)
#define z_pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) z_pllp(v)
/**
* @brief fill in pll configuration structure

8
drivers/clock_control/stm32l0x_ll_clock.c
View file

@ -17,11 +17,11 @@
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/* Macros to fill up multiplication and division factors values */
#define _pll_mul(v) LL_RCC_PLL_MUL_ ## v
#define pll_mul(v) _pll_mul(v)
#define z_pll_mul(v) LL_RCC_PLL_MUL_ ## v
#define pll_mul(v) z_pll_mul(v)
#define _pll_div(v) LL_RCC_PLL_DIV_ ## v
#define pll_div(v) _pll_div(v)
#define z_pll_div(v) LL_RCC_PLL_DIV_ ## v
#define pll_div(v) z_pll_div(v)
/**
* @brief Fill PLL configuration structure

8
drivers/clock_control/stm32l4x_ll_clock.c
View file

@ -17,11 +17,11 @@
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define _pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) _pllm(v)
#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) z_pllm(v)
#define _pllr(v) LL_RCC_PLLR_DIV_ ## v
#define pllr(v) _pllr(v)
#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
#define pllr(v) z_pllr(v)
/**
* @brief fill in pll configuration structure

4
drivers/counter/counter_imx_epit.c
View file

@ -152,7 +152,7 @@ static const struct counter_driver_api imx_epit_driver_api = {
#define COUNTER_IMX_EPIT_DEVICE(idx) \
static int imx_epit_config_func_##idx(struct device *dev); \
static const struct imx_epit_config imx_epit_##idx##_config = { \
static const struct imx_epit_config imx_epit_##idx##z_config = { \
.info = { \
.max_top_value = COUNTER_MAX_RELOAD, \
.freq = 1U, \
@ -165,7 +165,7 @@ static const struct imx_epit_config imx_epit_##idx##_config = { \
static struct imx_epit_data imx_epit_##idx##_data; \
DEVICE_AND_API_INIT(epit_##idx, DT_COUNTER_IMX_EPIT_##idx##_LABEL, \
&imx_epit_config_func_##idx, \
&imx_epit_##idx##_data, &imx_epit_##idx##_config.info, \
&imx_epit_##idx##_data, &imx_epit_##idx##z_config.info, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&imx_epit_driver_api); \
static int imx_epit_config_func_##idx(struct device *dev) \

10
drivers/counter/counter_nrfx_rtc.c
View file

@ -104,7 +104,7 @@ static int counter_nrfx_set_alarm(struct device *dev, u8_t chan_id,
return 0;
}
static void _disable(struct device *dev, u8_t id)
static void disable(struct device *dev, u8_t id)
{
const struct counter_nrfx_config *config = get_nrfx_config(dev);
@ -114,7 +114,7 @@ static void _disable(struct device *dev, u8_t id)
static int counter_nrfx_cancel_alarm(struct device *dev, u8_t chan_id)
{
_disable(dev, chan_id);
disable(dev, chan_id);
return 0;
}
@ -164,7 +164,7 @@ static void alarm_event_handler(struct device *dev, u32_t id)
cc_val = nrf_rtc_cc_get(config->rtc.p_reg, ID_TO_CC(id));
_disable(dev, id);
disable(dev, id);
clbk(dev, id, cc_val, config->ch_data[id].user_data);
}
@ -262,7 +262,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = {
static struct counter_nrfx_ch_data \
counter##idx##_ch_data[CC_TO_ID(RTC##idx##_CC_NUM)]; \
LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \
static const struct counter_nrfx_config nrfx_counter_##idx##_config = {\
static const struct counter_nrfx_config nrfx_counter_##idx##z_config = {\
.info = { \
.max_top_value = COUNTER_MAX_TOP_VALUE, \
.freq = RTC_CLOCK / \
@ -278,7 +278,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = {
DT_NORDIC_NRF_RTC_RTC_##idx##_LABEL, \
counter_##idx##_init, \
&counter_##idx##_data, \
&nrfx_counter_##idx##_config.info, \
&nrfx_counter_##idx##z_config.info, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&counter_nrfx_driver_api)

10
drivers/counter/counter_nrfx_timer.c
View file

@ -140,7 +140,7 @@ static int counter_nrfx_set_alarm(struct device *dev, u8_t chan_id,
return 0;
}
static void _disable(struct device *dev, u8_t id)
static void disable(struct device *dev, u8_t id)
{
const struct counter_nrfx_config *config = get_nrfx_config(dev);
@ -150,7 +150,7 @@ static void _disable(struct device *dev, u8_t id)
static int counter_nrfx_cancel_alarm(struct device *dev, u8_t chan_id)
{
_disable(dev, chan_id);
disable(dev, chan_id);
return 0;
}
@ -201,7 +201,7 @@ static void alarm_event_handler(struct device *dev, u32_t id)
}
cc_val = nrfx_timer_capture_get(&config->timer, ID_TO_CC(id));
_disable(dev, id);
disable(dev, id);
clbk(dev, id, cc_val, config->ch_data[id].user_data);
}
@ -271,7 +271,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = {
static struct counter_nrfx_ch_data \
counter##idx##_ch_data[CC_TO_ID(TIMER##idx##_CC_NUM)]; \
LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \
static const struct counter_nrfx_config nrfx_counter_##idx##_config = {\
static const struct counter_nrfx_config nrfx_counter_##idx##z_config = {\
.info = { \
.max_top_value = (TIMER##idx##_MAX_SIZE == 32) ? \
0xffffffff : 0x0000ffff, \
@ -288,7 +288,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = {
DT_NORDIC_NRF_TIMER_TIMER_##idx##_LABEL, \
counter_##idx##_init, \
&counter_##idx##_data, \
&nrfx_counter_##idx##_config.info, \
&nrfx_counter_##idx##z_config.info, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&counter_nrfx_driver_api)

30
drivers/display/grove_lcd_rgb.c
View file

@ -85,7 +85,7 @@ static u8_t color_define[][3] = {
/********************************************
* PRIVATE FUNCTIONS
*******************************************/
static void _rgb_reg_set(struct device * const i2c, u8_t addr, u8_t dta)
static void rgb_reg_set(struct device * const i2c, u8_t addr, u8_t dta)
{
u8_t data[2] = { addr, dta };
@ -93,7 +93,7 @@ static void _rgb_reg_set(struct device * const i2c, u8_t addr, u8_t dta)
}
static inline void _sleep(u32_t sleep_in_ms)
static inline void sleep(u32_t sleep_in_ms)
{
k_busy_wait(SLEEP_IN_US(sleep_in_ms));
}
@ -147,7 +147,7 @@ void glcd_clear(struct device *port)
i2c_write(dev->i2c, clear, sizeof(clear), rom->lcd_addr);
LOG_DBG("clear, delay 20 ms");
_sleep(20);
sleep(20);
}
@ -164,7 +164,7 @@ void glcd_display_state_set(struct device *port, u8_t opt)
i2c_write(dev->i2c, data, sizeof(data), rom->lcd_addr);
LOG_DBG("set display_state options, delay 5 ms");
_sleep(5);
sleep(5);
}
@ -215,9 +215,9 @@ void glcd_color_set(struct device *port, u8_t r, u8_t g, u8_t b)
{
struct glcd_data * const dev = port->driver_data;
_rgb_reg_set(dev->i2c, REGISTER_R, r);
_rgb_reg_set(dev->i2c, REGISTER_G, g);
_rgb_reg_set(dev->i2c, REGISTER_B, b);
rgb_reg_set(dev->i2c, REGISTER_R, r);
rgb_reg_set(dev->i2c, REGISTER_G, g);
rgb_reg_set(dev->i2c, REGISTER_B, b);
}
@ -233,7 +233,7 @@ void glcd_function_set(struct device *port, u8_t opt)
i2c_write(dev->i2c, data, sizeof(data), rom->lcd_addr);
LOG_DBG("set function options, delay 5 ms");
_sleep(5);
sleep(5);
}
@ -288,7 +288,7 @@ int glcd_initialize(struct device *port)
* VDD to power on, so pause a little here, 30 ms min, so we go 50
*/
LOG_DBG("delay 50 ms while the VDD powers on");
_sleep(50);
sleep(50);
/* Configure everything for the display function first */
cmd = GLCD_CMD_FUNCTION_SET | GLCD_FS_ROWS_2;
@ -309,15 +309,15 @@ int glcd_initialize(struct device *port)
/* Now power on the background RGB control */
LOG_INF("configuring the RGB background");
_rgb_reg_set(dev->i2c, 0x00, 0x00);
_rgb_reg_set(dev->i2c, 0x01, 0x05);
_rgb_reg_set(dev->i2c, 0x08, 0xAA);
rgb_reg_set(dev->i2c, 0x00, 0x00);
rgb_reg_set(dev->i2c, 0x01, 0x05);
rgb_reg_set(dev->i2c, 0x08, 0xAA);
/* Now set the background color to white */
LOG_DBG("background set to white");
_rgb_reg_set(dev->i2c, REGISTER_R, color_define[GROVE_RGB_WHITE][0]);
_rgb_reg_set(dev->i2c, REGISTER_G, color_define[GROVE_RGB_WHITE][1]);
_rgb_reg_set(dev->i2c, REGISTER_B, color_define[GROVE_RGB_WHITE][2]);
rgb_reg_set(dev->i2c, REGISTER_R, color_define[GROVE_RGB_WHITE][0]);
rgb_reg_set(dev->i2c, REGISTER_G, color_define[GROVE_RGB_WHITE][1]);
rgb_reg_set(dev->i2c, REGISTER_B, color_define[GROVE_RGB_WHITE][2]);
return 0;
}

2
drivers/display/mb_display.c
View file

@ -326,7 +326,7 @@ static void clear_display(struct k_timer *timer)
}
static struct mb_display display = {
.timer = _K_TIMER_INITIALIZER(display.timer, show_row, clear_display),
.timer = Z_TIMER_INITIALIZER(display.timer, show_row, clear_display),
};
static void start_scroll(struct mb_display *disp, s32_t duration)

4
drivers/ethernet/eth_enc28j60.c
View file

@ -751,9 +751,9 @@ static struct eth_enc28j60_runtime eth_enc28j60_0_runtime = {
DT_MICROCHIP_ENC28J60_0_LOCAL_MAC_ADDRESS_4,
DT_MICROCHIP_ENC28J60_0_LOCAL_MAC_ADDRESS_5
},
.tx_rx_sem = _K_SEM_INITIALIZER(eth_enc28j60_0_runtime.tx_rx_sem,
.tx_rx_sem = Z_SEM_INITIALIZER(eth_enc28j60_0_runtime.tx_rx_sem,
1, UINT_MAX),
.int_sem = _K_SEM_INITIALIZER(eth_enc28j60_0_runtime.int_sem,
.int_sem = Z_SEM_INITIALIZER(eth_enc28j60_0_runtime.int_sem,
0, UINT_MAX),
};

6
drivers/flash/flash_page_layout.c
View file

@ -6,7 +6,7 @@
#include <flash.h>
static int _flash_get_page_info(struct device *dev, off_t offs,
static int flash_get_page_info(struct device *dev, off_t offs,
bool use_addr, struct flash_pages_info *info)
{
const struct flash_driver_api *api = dev->driver_api;
@ -55,13 +55,13 @@ static int _flash_get_page_info(struct device *dev, off_t offs,
int z_impl_flash_get_page_info_by_offs(struct device *dev, off_t offs,
struct flash_pages_info *info)
{
return _flash_get_page_info(dev, offs, true, info);
return flash_get_page_info(dev, offs, true, info);
}
int z_impl_flash_get_page_info_by_idx(struct device *dev, u32_t page_index,
struct flash_pages_info *info)
{
return _flash_get_page_info(dev, page_index, false, info);
return flash_get_page_info(dev, page_index, false, info);
}
size_t z_impl_flash_get_page_count(struct device *dev)

10
drivers/gpio/gpio_atmel_sam3.c
View file

@ -33,7 +33,7 @@ struct gpio_sam3_runtime {
sys_slist_t cb;
};
static void _config(struct device *dev, u32_t mask, int flags)
static void config(struct device *dev, u32_t mask, int flags)
{
const struct gpio_sam3_config *cfg = dev->config->config_info;
@ -101,10 +101,10 @@ static int gpio_sam3_config(struct device *dev, int access_op,
{
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
_config(dev, BIT(pin), flags);
config(dev, BIT(pin), flags);
break;
case GPIO_ACCESS_BY_PORT:
_config(dev, (0xFFFFFFFF), flags);
config(dev, (0xFFFFFFFF), flags);
break;
default:
return -ENOTSUP;
@ -193,7 +193,7 @@ static void gpio_sam3_isr(void *arg)
int_stat = cfg->port->PIO_ISR;
_gpio_fire_callbacks(&context->cb, dev, int_stat);
gpio_fire_callbacks(&context->cb, dev, int_stat);
}
static int gpio_sam3_manage_callback(struct device *dev,
@ -202,7 +202,7 @@ static int gpio_sam3_manage_callback(struct device *dev,
{
struct gpio_sam3_runtime *context = dev->driver_data;
return _gpio_manage_callback(&context->cb, callback, set);
return gpio_manage_callback(&context->cb, callback, set);
}
static int gpio_sam3_enable_callback(struct device *dev,

4
drivers/gpio/gpio_cc2650.c
View file

@ -200,7 +200,7 @@ static void gpio_cc2650_isr(void *arg)
sys_write32(evflags | call_mask, evflags31_0);
_gpio_fire_callbacks(&data->callbacks, dev, call_mask);
gpio_fire_callbacks(&data->callbacks, dev, call_mask);
}
@ -297,7 +297,7 @@ static int gpio_cc2650_manage_callback(struct device *port,
{
struct gpio_cc2650_data *data = port->driver_data;
return _gpio_manage_callback(&data->callbacks, callback, set);
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int gpio_cc2650_enable_callback(struct device *port,

4
drivers/gpio/gpio_cc32xx.c
View file

@ -129,7 +129,7 @@ static int gpio_cc32xx_manage_callback(struct device *dev,
{
struct gpio_cc32xx_data *data = DEV_DATA(dev);
return _gpio_manage_callback(&data->callbacks, callback, set);
return gpio_manage_callback(&data->callbacks, callback, set);
}
@ -179,7 +179,7 @@ static void gpio_cc32xx_port_isr(void *arg)
MAP_GPIOIntClear(config->port_base, int_status);
/* Call the registered callbacks */
_gpio_fire_callbacks(&data->callbacks, (struct device *)dev,
gpio_fire_callbacks(&data->callbacks, (struct device *)dev,
enabled_int);
/* Re-enable the interrupts */

4
drivers/gpio/gpio_cmsdk_ahb.c
View file

@ -209,7 +209,7 @@ static void gpio_cmsdk_ahb_isr(void *arg)
int_stat = cfg->port->intstatus;
_gpio_fire_callbacks(&data->gpio_cb, dev, int_stat);
gpio_fire_callbacks(&data->gpio_cb, dev, int_stat);
/* clear the port interrupts */
cfg->port->intclear = 0xFFFFFFFF;
@ -221,7 +221,7 @@ static int gpio_cmsdk_ahb_manage_callback(struct device *dev,
{
struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;
return _gpio_manage_callback(&data->gpio_cb, callback, set);
return gpio_manage_callback(&data->gpio_cb, callback, set);
}
static int gpio_cmsdk_ahb_enable_callback(struct device *dev,

22
drivers/gpio/gpio_dw.c
View file

@ -79,7 +79,7 @@ static void dw_set_bit(u32_t base_addr, u32_t offset,
#endif
#ifdef CONFIG_GPIO_DW_CLOCK_GATE
static inline void _gpio_dw_clock_config(struct device *port)
static inline void gpio_dw_clock_config(struct device *port)
{
char *drv = CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME;
struct device *clk;
@ -92,7 +92,7 @@ static inline void _gpio_dw_clock_config(struct device *port)
}
}
static inline void _gpio_dw_clock_on(struct device *port)
static inline void gpio_dw_clock_on(struct device *port)
{
const struct gpio_dw_config *config = port->config->config_info;
struct gpio_dw_runtime *context = port->driver_data;
@ -100,7 +100,7 @@ static inline void _gpio_dw_clock_on(struct device *port)
clock_control_on(context->clock, config->clock_data);
}
static inline void _gpio_dw_clock_off(struct device *port)
static inline void gpio_dw_clock_off(struct device *port)
{
const struct gpio_dw_config *config = port->config->config_info;
struct gpio_dw_runtime *context = port->driver_data;
@ -108,9 +108,9 @@ static inline void _gpio_dw_clock_off(struct device *port)
clock_control_off(context->clock, config->clock_data);
}
#else
#define _gpio_dw_clock_config(...)
#define _gpio_dw_clock_on(...)
#define _gpio_dw_clock_off(...)
#define gpio_dw_clock_config(...)
#define gpio_dw_clock_on(...)
#define gpio_dw_clock_off(...)
#endif
#ifdef CONFIG_SOC_QUARK_SE_C1000_SS
@ -291,7 +291,7 @@ static inline int gpio_dw_manage_callback(struct device *port,
{
struct gpio_dw_runtime *context = port->driver_data;
return _gpio_manage_callback(&context->callbacks, callback, set);
return gpio_manage_callback(&context->callbacks, callback, set);
}
static inline int gpio_dw_enable_callback(struct device *port, int access_op,
@ -345,7 +345,7 @@ static u32_t gpio_dw_get_power_state(struct device *port)
static inline int gpio_dw_suspend_port(struct device *port)
{
_gpio_dw_clock_off(port);
gpio_dw_clock_off(port);
gpio_dw_set_power_state(port, DEVICE_PM_SUSPEND_STATE);
return 0;
@ -353,7 +353,7 @@ static inline int gpio_dw_suspend_port(struct device *port)
static inline int gpio_dw_resume_from_suspend_port(struct device *port)
{
_gpio_dw_clock_on(port);
gpio_dw_clock_on(port);
gpio_dw_set_power_state(port, DEVICE_PM_ACTIVE_STATE);
return 0;
}
@ -422,7 +422,7 @@ static void gpio_dw_isr(void *arg)
dw_write(base_addr, PORTA_EOI, int_status);
_gpio_fire_callbacks(&context->callbacks, port, int_status);
gpio_fire_callbacks(&context->callbacks, port, int_status);
}
static const struct gpio_driver_api api_funcs = {
@ -481,7 +481,7 @@ static int gpio_dw_initialize(struct device *port)
/* interrupts in sync with system clock */
dw_set_bit(base_addr, INT_CLOCK_SYNC, LS_SYNC_POS, 1);
_gpio_dw_clock_config(port);
gpio_dw_clock_config(port);
/* mask and disable interrupts */
dw_write(base_addr, INTMASK, ~(0));

4
drivers/gpio/gpio_esp32.c
View file

@ -210,7 +210,7 @@ static int gpio_esp32_manage_callback(struct device *dev,
{
struct gpio_esp32_data *data = dev->driver_data;
return _gpio_manage_callback(&data->cb, callback, set);
return gpio_manage_callback(&data->cb, callback, set);
}
static int gpio_esp32_enable_callback(struct device *dev,
@ -247,7 +247,7 @@ static void gpio_esp32_fire_callbacks(struct device *device)
u32_t values = *data->port.irq.status_reg;
if (values & data->cb_pins) {
_gpio_fire_callbacks(&data->cb, device, values);
gpio_fire_callbacks(&data->cb, device, values);
}
*data->port.irq.ack_reg = values;

4
drivers/gpio/gpio_gecko.c
View file

@ -192,7 +192,7 @@ static int gpio_gecko_manage_callback(struct device *dev,
{
struct gpio_gecko_data *data = dev->driver_data;
return _gpio_manage_callback(&data->callbacks, callback, set);
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int gpio_gecko_enable_callback(struct device *dev,
@ -244,7 +244,7 @@ static void gpio_gecko_common_isr(void *arg)
enabled_int = int_status & port_data->pin_callback_enables;
int_status &= ~enabled_int;
_gpio_fire_callbacks(&port_data->callbacks, port_dev,
gpio_fire_callbacks(&port_data->callbacks, port_dev,
enabled_int);
}
/* Clear the pending interrupts */

4
drivers/gpio/gpio_imx.c
View file

@ -109,7 +109,7 @@ static int imx_gpio_manage_callback(struct device *dev,
{
struct imx_gpio_data *data = dev->driver_data;
return _gpio_manage_callback(&data->callbacks, callback, set);
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int imx_gpio_enable_callback(struct device *dev,
@ -163,7 +163,7 @@ static void imx_gpio_port_isr(void *arg)
int_flags = GPIO_ISR_REG(config->base);
enabled_int = int_flags & data->pin_callback_enables;
_gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
GPIO_ISR_REG(config->base) = enabled_int;
}

2
drivers/gpio/gpio_intel_apl.c
View file

@ -360,7 +360,7 @@ static int gpio_intel_apl_manage_callback(struct device *dev,
{
struct gpio_intel_apl_data *data = dev->driver_data;
return _gpio_manage_callback(&data->cb, callback, set);
return gpio_manage_callback(&data->cb, callback, set);
}
static int gpio_intel_apl_enable_callback(struct device *dev,

4
drivers/gpio/gpio_mcux.c
View file

@ -179,7 +179,7 @@ static int gpio_mcux_manage_callback(struct device *dev,
{
struct gpio_mcux_data *data = dev->driver_data;
return _gpio_manage_callback(&data->callbacks, callback, set);
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int gpio_mcux_enable_callback(struct device *dev,
@ -220,7 +220,7 @@ static void gpio_mcux_port_isr(void *arg)
int_status = config->port_base->ISFR;
enabled_int = int_status & data->pin_callback_enables;
_gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
/* Clear the port interrupts */
config->port_base->ISFR = 0xFFFFFFFF;

4
drivers/gpio/gpio_mcux_igpio.c
View file

@ -107,7 +107,7 @@ static int mcux_igpio_manage_callback(struct device *dev,
{
struct mcux_igpio_data *data = dev->driver_data;
return _gpio_manage_callback(&data->callbacks, callback, set);
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int mcux_igpio_enable_callback(struct device *dev,
@ -154,7 +154,7 @@ static void mcux_igpio_port_isr(void *arg)
int_flags = GPIO_PortGetInterruptFlags(config->base);
enabled_int = int_flags & data->pin_callback_enables;
_gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
GPIO_ClearPinsInterruptFlags(config->base, enabled_int);
}

4
drivers/gpio/gpio_nrfx.c
View file

@ -257,7 +257,7 @@ static int gpio_nrfx_manage_callback(struct device *port,
struct gpio_callback *callback,
bool set)
{
return _gpio_manage_callback(&get_port_data(port)->callbacks,
return gpio_manage_callback(&get_port_data(port)->callbacks,
callback, set);
}
@ -400,7 +400,7 @@ static u32_t check_level_trigger_pins(struct device *port)
static inline void fire_callbacks(struct device *port, u32_t pins)
{
_gpio_fire_callbacks(&get_port_data(port)->callbacks, port, pins);
gpio_fire_callbacks(&get_port_data(port)->callbacks, port, pins);
}
#ifdef CONFIG_GPIO_NRF_P0

36
drivers/gpio/gpio_pcal9535a.c
View file

@ -54,7 +54,7 @@ LOG_MODULE_REGISTER(gpio_pcal9535a);
* @param dev Device struct.
* @return 1 if I2C master is identified, 0 if not.
*/
static inline int _has_i2c_master(struct device *dev)
static inline int has_i2c_master(struct device *dev)
{
struct gpio_pcal9535a_drv_data * const drv_data =
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
@ -77,7 +77,7 @@ static inline int _has_i2c_master(struct device *dev)
*
* @return 0 if successful, failed otherwise.
*/
static int _read_port_regs(struct device *dev, u8_t reg,
static int read_port_regs(struct device *dev, u8_t reg,
union gpio_pcal9535a_port_data *buf)
{
const struct gpio_pcal9535a_config * const config =
@ -113,7 +113,7 @@ error:
*
* @return 0 if successful, failed otherwise.
*/
static int _write_port_regs(struct device *dev, u8_t reg,
static int write_port_regs(struct device *dev, u8_t reg,
union gpio_pcal9535a_port_data *buf)
{
const struct gpio_pcal9535a_config * const config =
@ -147,7 +147,7 @@ static int _write_port_regs(struct device *dev, u8_t reg,
*
* @return 0 if successful, failed otherwise
*/
static int _setup_pin_dir(struct device *dev, int access_op,
static int setup_pin_dir(struct device *dev, int access_op,
u32_t pin, int flags)
{
struct gpio_pcal9535a_drv_data * const drv_data =
@ -183,7 +183,7 @@ static int _setup_pin_dir(struct device *dev, int access_op,
goto done;
}
ret = _write_port_regs(dev, REG_CONF_PORT0, port);
ret = write_port_regs(dev, REG_CONF_PORT0, port);
done:
return ret;
@ -199,7 +199,7 @@ done:
*
* @return 0 if successful, failed otherwise
*/
static int _setup_pin_pullupdown(struct device *dev, int access_op,
static int setup_pin_pullupdown(struct device *dev, int access_op,
u32_t pin, int flags)
{
struct gpio_pcal9535a_drv_data * const drv_data =
@ -244,7 +244,7 @@ static int _setup_pin_pullupdown(struct device *dev, int access_op,
goto done;
}
ret = _write_port_regs(dev, REG_PUD_SEL_PORT0, port);
ret = write_port_regs(dev, REG_PUD_SEL_PORT0, port);
if (ret) {
goto done;
}
@ -276,7 +276,7 @@ en_dis:
goto done;
}
ret = _write_port_regs(dev, REG_PUD_EN_PORT0, port);
ret = write_port_regs(dev, REG_PUD_EN_PORT0, port);
done:
return ret;
@ -292,7 +292,7 @@ done:
*
* @return 0 if successful, failed otherwise
*/
static int _setup_pin_polarity(struct device *dev, int access_op,
static int setup_pin_polarity(struct device *dev, int access_op,
u32_t pin, int flags)
{
struct gpio_pcal9535a_drv_data * const drv_data =
@ -328,7 +328,7 @@ static int _setup_pin_polarity(struct device *dev, int access_op,
goto done;
}
ret = _write_port_regs(dev, REG_POL_INV_PORT0, port);
ret = write_port_regs(dev, REG_POL_INV_PORT0, port);
if (!ret) {
drv_data->out_pol_inv = port->all;
}
@ -362,25 +362,25 @@ static int gpio_pcal9535a_config(struct device *dev, int access_op,
return -ENOTSUP;
}
if (!_has_i2c_master(dev)) {
if (!has_i2c_master(dev)) {
return -EINVAL;
}
ret = _setup_pin_dir(dev, access_op, pin, flags);
ret = setup_pin_dir(dev, access_op, pin, flags);
if (ret) {
LOG_ERR("PCAL9535A[0x%X]: error setting pin direction (%d)",
i2c_addr, ret);
goto done;
}
ret = _setup_pin_polarity(dev, access_op, pin, flags);
ret = setup_pin_polarity(dev, access_op, pin, flags);
if (ret) {
LOG_ERR("PCAL9535A[0x%X]: error setting pin polarity (%d)",
i2c_addr, ret);
goto done;
}
ret = _setup_pin_pullupdown(dev, access_op, pin, flags);
ret = setup_pin_pullupdown(dev, access_op, pin, flags);
if (ret) {
LOG_ERR("PCAL9535A[0x%X]: error setting pin pull up/down "
"(%d)", i2c_addr, ret);
@ -411,7 +411,7 @@ static int gpio_pcal9535a_write(struct device *dev, int access_op,
u16_t new_value;
int ret;
if (!_has_i2c_master(dev)) {
if (!has_i2c_master(dev)) {
return -EINVAL;
}
@ -445,7 +445,7 @@ static int gpio_pcal9535a_write(struct device *dev, int access_op,
goto done;
}
ret = _write_port_regs(dev, REG_OUTPUT_PORT0, port);
ret = write_port_regs(dev, REG_OUTPUT_PORT0, port);
done:
return ret;
@ -467,11 +467,11 @@ static int gpio_pcal9535a_read(struct device *dev, int access_op,
union gpio_pcal9535a_port_data buf;
int ret;
if (!_has_i2c_master(dev)) {
if (!has_i2c_master(dev)) {
return -EINVAL;
}
ret = _read_port_regs(dev, REG_INPUT_PORT0, &buf);
ret = read_port_regs(dev, REG_INPUT_PORT0, &buf);
if (ret != 0) {
goto done;
}

4
drivers/gpio/gpio_qmsi.c
View file

@ -176,7 +176,7 @@ static void gpio_qmsi_callback(void *data, u32_t status)
const u32_t enabled_mask = context->pin_callbacks & status;
if (enabled_mask) {
_gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
}
}
@ -307,7 +307,7 @@ static inline int gpio_qmsi_manage_callback(struct device *port,
{
struct gpio_qmsi_runtime *context = port->driver_data;
return _gpio_manage_callback(&context->callbacks, callback, set);
return gpio_manage_callback(&context->callbacks, callback, set);
}
static inline int gpio_qmsi_enable_callback(struct device *port,

4
drivers/gpio/gpio_qmsi_ss.c
View file

@ -145,7 +145,7 @@ static void ss_gpio_qmsi_callback(void *data, uint32_t status)
const u32_t enabled_mask = context->pin_callbacks & status;
if (enabled_mask) {
_gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
}
}
@ -296,7 +296,7 @@ static inline int ss_gpio_qmsi_manage_callback(struct device *port,
{
struct ss_gpio_qmsi_runtime *context = port->driver_data;
return _gpio_manage_callback(&context->callbacks, callback, set);
return gpio_manage_callback(&context->callbacks, callback, set);
}
static inline int ss_gpio_qmsi_enable_callback(struct device *port,

4
drivers/gpio/gpio_rv32m1.c
View file

@ -179,7 +179,7 @@ static int gpio_rv32m1_manage_callback(struct device *dev,
{
struct gpio_rv32m1_data *data = dev->driver_data;
_gpio_manage_callback(&data->callbacks, callback, set);
gpio_manage_callback(&data->callbacks, callback, set);
return 0;
}
@ -222,7 +222,7 @@ static void gpio_rv32m1_port_isr(void *arg)
int_status = config->port_base->ISFR;
enabled_int = int_status & data->pin_callback_enables;
_gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
/* Clear the port interrupts */
config->port_base->ISFR = 0xFFFFFFFF;

4
drivers/gpio/gpio_sam.c
View file

@ -193,7 +193,7 @@ static void gpio_sam_isr(void *arg)
int_stat = pio->PIO_ISR;
_gpio_fire_callbacks(&context->cb, dev, int_stat);
gpio_fire_callbacks(&context->cb, dev, int_stat);
}
static int gpio_sam_manage_callback(struct device *port,
@ -202,7 +202,7 @@ static int gpio_sam_manage_callback(struct device *port,
{
struct gpio_sam_runtime *context = port->driver_data;
return _gpio_manage_callback(&context->cb, callback, set);
return gpio_manage_callback(&context->cb, callback, set);
}
static int gpio_sam_enable_callback(struct device *port,

90
drivers/gpio/gpio_sch.c
View file

@ -27,26 +27,26 @@ LOG_MODULE_REGISTER(gpio_sch);
* memory mapped I/O.
*/
#ifdef GPIO_SCH_LEGACY_IO_PORTS_ACCESS
#define _REG_READ sys_in32
#define _REG_WRITE sys_out32
#define _REG_SET_BIT sys_io_set_bit
#define _REG_CLEAR_BIT sys_io_clear_bit
#define Z_REG_READ sys_in32
#define Z_REG_WRITE sys_out32
#define Z_REG_SET_BIT sys_io_set_bit
#define Z_REG_CLEAR_BIT sys_io_clear_bit
#else
#define _REG_READ sys_read32
#define _REG_WRITE sys_write32
#define _REG_SET_BIT sys_set_bit
#define _REG_CLEAR_BIT sys_clear_bit
#define Z_REG_READ sys_read32
#define Z_REG_WRITE sys_write32
#define Z_REG_SET_BIT sys_set_bit
#define Z_REG_CLEAR_BIT sys_clear_bit
#endif /* GPIO_SCH_LEGACY_IO_PORTS_ACCESS */
#define DEFINE_MM_REG_READ(__reg, __off) \
static inline u32_t _read_##__reg(u32_t addr) \
static inline u32_t z_read_##__reg(u32_t addr) \
{ \
return _REG_READ(addr + __off); \
return Z_REG_READ(addr + __off); \
}
#define DEFINE_MM_REG_WRITE(__reg, __off) \
static inline void _write_##__reg(u32_t data, u32_t addr) \
static inline void z_write_##__reg(u32_t data, u32_t addr) \
{ \
_REG_WRITE(data, addr + __off); \
Z_REG_WRITE(data, addr + __off); \
}
DEFINE_MM_REG_READ(glvl, GPIO_SCH_REG_GLVL)
@ -56,21 +56,21 @@ DEFINE_MM_REG_WRITE(gtne, GPIO_SCH_REG_GTNE)
DEFINE_MM_REG_READ(gts, GPIO_SCH_REG_GTS)
DEFINE_MM_REG_WRITE(gts, GPIO_SCH_REG_GTS)
static void _set_bit(u32_t base_addr,
static void set_bit(u32_t base_addr,
u32_t bit, u8_t set)
{
if (!set) {
_REG_CLEAR_BIT(base_addr, bit);
Z_REG_CLEAR_BIT(base_addr, bit);
} else {
_REG_SET_BIT(base_addr, bit);
Z_REG_SET_BIT(base_addr, bit);
}
}
#define DEFINE_MM_REG_SET_BIT(__reg, __off) \
static inline void _set_bit_##__reg(u32_t addr, \
static inline void z_set_bit_##__reg(u32_t addr, \
u32_t bit, u8_t set) \
{ \
_set_bit(addr + __off, bit, set); \
set_bit(addr + __off, bit, set); \
}
DEFINE_MM_REG_SET_BIT(gen, GPIO_SCH_REG_GEN)
@ -79,21 +79,21 @@ DEFINE_MM_REG_SET_BIT(glvl, GPIO_SCH_REG_GLVL)
DEFINE_MM_REG_SET_BIT(gtpe, GPIO_SCH_REG_GTPE)
DEFINE_MM_REG_SET_BIT(gtne, GPIO_SCH_REG_GTNE)
static inline void _set_data_reg(u32_t *reg, u8_t pin, u8_t set)
static inline void set_data_reg(u32_t *reg, u8_t pin, u8_t set)
{
*reg &= ~(BIT(pin));
*reg |= (set << pin) & BIT(pin);
}
static void _gpio_pin_config(struct device *dev, u32_t pin, int flags)
static void gpio_pin_config(struct device *dev, u32_t pin, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data;
u8_t active_high = 0U;
u8_t active_low = 0U;
_set_bit_gen(info->regs, pin, 1);
_set_bit_gio(info->regs, pin, !(flags & GPIO_DIR_MASK));
z_set_bit_gen(info->regs, pin, 1);
z_set_bit_gio(info->regs, pin, !(flags & GPIO_DIR_MASK));
if (flags & GPIO_INT) {
if (flags & GPIO_INT_DOUBLE_EDGE) {
@ -112,17 +112,17 @@ static void _gpio_pin_config(struct device *dev, u32_t pin, int flags)
/* We store the gtpe/gtne settings. These will be used once
* we enable the callback for the pin, or the whole port
*/
_set_data_reg(&gpio->int_regs.gtpe, pin, active_high);
_set_data_reg(&gpio->int_regs.gtne, pin, active_low);
set_data_reg(&gpio->int_regs.gtpe, pin, active_high);
set_data_reg(&gpio->int_regs.gtne, pin, active_low);
}
static inline void _gpio_port_config(struct device *dev, int flags)
static inline void gpio_port_config(struct device *dev, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
int pin;
for (pin = 0; pin < info->bits; pin++) {
_gpio_pin_config(dev, pin, flags);
gpio_pin_config(dev, pin, flags);
}
}
@ -144,9 +144,9 @@ static int gpio_sch_config(struct device *dev,
return -EINVAL;
}
_gpio_pin_config(dev, pin, flags);
gpio_pin_config(dev, pin, flags);
} else {
_gpio_port_config(dev, flags);
gpio_port_config(dev, flags);
}
return 0;
@ -162,9 +162,9 @@ static int gpio_sch_write(struct device *dev,
return -ENOTSUP;
}
_set_bit_glvl(info->regs, pin, value);
z_set_bit_glvl(info->regs, pin, value);
} else {
_write_glvl(info->regs, value);
z_write_glvl(info->regs, value);
}
return 0;
@ -175,7 +175,7 @@ static int gpio_sch_read(struct device *dev,
{
const struct gpio_sch_config *info = dev->config->config_info;
*value = _read_glvl(info->regs);
*value = z_read_glvl(info->regs);
if (access_op == GPIO_ACCESS_BY_PIN) {
if (pin >= info->bits) {
@ -188,7 +188,7 @@ static int gpio_sch_read(struct device *dev,
return 0;
}
static void _gpio_sch_poll_status(void *arg1, void *unused1, void *unused2)
static void gpio_sch_poll_status(void *arg1, void *unused1, void *unused2)
{
struct device *dev = (struct device *)arg1;
const struct gpio_sch_config *info = dev->config->config_info;
@ -198,22 +198,22 @@ static void _gpio_sch_poll_status(void *arg1, void *unused1, void *unused2)
ARG_UNUSED(unused2);
/* Cleaning up GTS first */
_write_gts(_read_gts(info->regs), info->regs);
z_write_gts(z_read_gts(info->regs), info->regs);
while (gpio->poll) {
u32_t status;
status = _read_gts(info->regs);
status = z_read_gts(info->regs);
if (!status) {
goto loop;
}
_gpio_fire_callbacks(&gpio->callbacks, dev, status);
gpio_fire_callbacks(&gpio->callbacks, dev, status);
/* It's not documented but writing the same status value
* into GTS tells to the controller it got handled.
*/
_write_gts(status, info->regs);
z_write_gts(status, info->regs);
loop:
k_timer_start(&gpio->poll_timer, GPIO_SCH_POLLING_MSEC, 0);
k_timer_status_sync(&gpio->poll_timer);
@ -232,7 +232,7 @@ static void _gpio_sch_manage_callback(struct device *dev)
k_thread_create(&gpio->polling_thread,
gpio->polling_stack,
GPIO_SCH_POLLING_STACK_SIZE,
(k_thread_entry_t)_gpio_sch_poll_status,
(k_thread_entry_t)gpio_sch_poll_status,
dev, NULL, NULL,
K_PRIO_COOP(1), 0, 0);
}
@ -246,7 +246,7 @@ static int gpio_sch_manage_callback(struct device *dev,
{
struct gpio_sch_data *gpio = dev->driver_data;
if (_gpio_manage_callback(&gpio->callbacks, callback, set)) {
if (gpio_manage_callback(&gpio->callbacks, callback, set)) {
return -EINVAL;
}
@ -268,13 +268,13 @@ static int gpio_sch_enable_callback(struct device *dev,
return -ENOTSUP;
}
_set_bit_gtpe(info->regs, pin, !!(bits & gpio->int_regs.gtpe));
_set_bit_gtne(info->regs, pin, !!(bits & gpio->int_regs.gtne));
z_set_bit_gtpe(info->regs, pin, !!(bits & gpio->int_regs.gtpe));
z_set_bit_gtne(info->regs, pin, !!(bits & gpio->int_regs.gtne));
gpio->cb_enabled |= bits;
} else {
_write_gtpe(gpio->int_regs.gtpe, info->regs);
_write_gtne(gpio->int_regs.gtne, info->regs);
z_write_gtpe(gpio->int_regs.gtpe, info->regs);
z_write_gtne(gpio->int_regs.gtne, info->regs);
gpio->cb_enabled = BIT_MASK(info->bits);
}
@ -295,13 +295,13 @@ static int gpio_sch_disable_callback(struct device *dev,
return -ENOTSUP;
}
_set_bit_gtpe(info->regs, pin, 0);
_set_bit_gtne(info->regs, pin, 0);
z_set_bit_gtpe(info->regs, pin, 0);
z_set_bit_gtne(info->regs, pin, 0);
gpio->cb_enabled &= ~BIT(pin);
} else {
_write_gtpe(0, info->regs);
_write_gtne(0, info->regs);
z_write_gtpe(0, info->regs);
z_write_gtne(0, info->regs);
gpio->cb_enabled = 0U;
}

4
drivers/gpio/gpio_sifive.c
View file

@ -72,7 +72,7 @@ static void gpio_sifive_irq_handler(void *arg)
(cfg->gpio_irq_base - RISCV_MAX_GENERIC_IRQ));
/* Call the corresponding callback registered for the pin */
_gpio_fire_callbacks(&data->cb, dev, pin_mask);
gpio_fire_callbacks(&data->cb, dev, pin_mask);
/*
* Write to either the rise_ip, fall_ip, high_ip or low_ip registers
@ -274,7 +274,7 @@ static int gpio_sifive_manage_callback(struct device *dev,
{
struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
return _gpio_manage_callback(&data->cb, callback, set);
return gpio_manage_callback(&data->cb, callback, set);
}
static int gpio_sifive_enable_callback(struct device *dev,

4
drivers/gpio/gpio_stellaris.c
View file

@ -66,7 +66,7 @@ static void gpio_stellaris_isr(void *arg)
u32_t base = cfg->base;
u32_t int_stat = sys_read32(GPIO_REG_ADDR(base, GPIO_MIS_OFFSET));
_gpio_fire_callbacks(&context->cb, dev, int_stat);
gpio_fire_callbacks(&context->cb, dev, int_stat);
sys_write32(int_stat, GPIO_REG_ADDR(base, GPIO_ICR_OFFSET));
}
@ -214,7 +214,7 @@ static int gpio_stellaris_manage_callback(struct device *dev,
{
struct gpio_stellaris_runtime *context = DEV_DATA(dev);
_gpio_manage_callback(&context->cb, callback, set);
gpio_manage_callback(&context->cb, callback, set);
return 0;
}

4
drivers/gpio/gpio_stm32.c
View file

@ -32,7 +32,7 @@ static void gpio_stm32_isr(int line, void *arg)
struct gpio_stm32_data *data = dev->driver_data;
if ((BIT(line) & data->cb_pins) != 0) {
_gpio_fire_callbacks(&data->cb, dev, BIT(line));
gpio_fire_callbacks(&data->cb, dev, BIT(line));
}
}
@ -340,7 +340,7 @@ static int gpio_stm32_manage_callback(struct device *dev,
{
struct gpio_stm32_data *data = dev->driver_data;
return _gpio_manage_callback(&data->cb, callback, set);
return gpio_manage_callback(&data->cb, callback, set);
}
static int gpio_stm32_enable_callback(struct device *dev,

2
drivers/gpio/gpio_sx1509b.c
View file

@ -363,7 +363,7 @@ static const struct gpio_sx1509b_config gpio_sx1509b_cfg = {
};
static struct gpio_sx1509b_drv_data gpio_sx1509b_drvdata = {
.lock = _K_SEM_INITIALIZER(gpio_sx1509b_drvdata.lock, 1, 1),
.lock = Z_SEM_INITIALIZER(gpio_sx1509b_drvdata.lock, 1, 1),
};
static const struct gpio_driver_api gpio_sx1509b_drv_api_funcs = {

4
drivers/gpio/gpio_utils.h
View file

@ -21,7 +21,7 @@
*
* @return 0 on success, negative errno otherwise.
*/
static inline int _gpio_manage_callback(sys_slist_t *callbacks,
static inline int gpio_manage_callback(sys_slist_t *callbacks,
struct gpio_callback *callback,
bool set)
{
@ -50,7 +50,7 @@ static inline int _gpio_manage_callback(sys_slist_t *callbacks,
* @param port A pointer on the gpio driver instance
* @param pins The actual pin mask that triggered the interrupt
*/
static inline void _gpio_fire_callbacks(sys_slist_t *list,
static inline void gpio_fire_callbacks(sys_slist_t *list,
struct device *port,
u32_t pins)
{

2
drivers/i2c/i2c-priv.h
View file

@ -15,7 +15,7 @@ extern "C" {
#include <dt-bindings/i2c/i2c.h>
#include <logging/log.h>
static inline u32_t _i2c_map_dt_bitrate(u32_t bitrate)
static inline u32_t i2c_map_dt_bitrate(u32_t bitrate)
{
switch (bitrate) {
case I2C_BITRATE_STANDARD:

14
drivers/i2c/i2c_cc32xx.c
View file

@ -109,7 +109,7 @@ static int i2c_cc32xx_configure(struct device *dev, u32_t dev_config_raw)
return 0;
}
static void _i2c_cc32xx_prime_transfer(struct device *dev, struct i2c_msg *msg,
static void i2c_cc32xx_prime_transfer(struct device *dev, struct i2c_msg *msg,
u16_t addr)
{
struct i2c_cc32xx_data *data = DEV_DATA(dev);
@ -167,7 +167,7 @@ static int i2c_cc32xx_transfer(struct device *dev, struct i2c_msg *msgs,
for (int i = 0; i < num_msgs; i++) {
/* Begin the transfer */
_i2c_cc32xx_prime_transfer(dev, msgs, addr);
i2c_cc32xx_prime_transfer(dev, msgs, addr);
/* Wait for the transfer to complete */
k_sem_take(&data->transfer_complete, K_FOREVER);
@ -188,7 +188,7 @@ static int i2c_cc32xx_transfer(struct device *dev, struct i2c_msg *msgs,
return retval;
}
static void _i2c_cc32xx_isr_handle_write(u32_t base,
static void i2c_cc32xx_isr_handle_write(u32_t base,
struct i2c_cc32xx_data *data)
{
/* Decrement write Counter */
@ -225,7 +225,7 @@ static void _i2c_cc32xx_isr_handle_write(u32_t base,
}
}
static void _i2c_cc32xx_isr_handle_read(u32_t base,
static void i2c_cc32xx_isr_handle_read(u32_t base,
struct i2c_cc32xx_data *data)
{
@ -307,10 +307,10 @@ static void i2c_cc32xx_isr(void *arg)
/* Handle (read or write) transmit complete: */
} else if (int_status & (I2C_MASTER_INT_DATA | I2C_MASTER_INT_START)) {
if (data->state == I2C_CC32XX_WRITE_MODE) {
_i2c_cc32xx_isr_handle_write(base, data);
i2c_cc32xx_isr_handle_write(base, data);
}
if (data->state == I2C_CC32XX_READ_MODE) {
_i2c_cc32xx_isr_handle_read(base, data);
i2c_cc32xx_isr_handle_read(base, data);
}
/* Some unanticipated H/W state: */
} else {
@ -347,7 +347,7 @@ static int i2c_cc32xx_init(struct device *dev)
HWREG(COMMON_REG_BASE) = regval;
/* Set to default configuration: */
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = i2c_cc32xx_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (error) {
return error;

22
drivers/i2c/i2c_dw.c
View file

@ -38,7 +38,7 @@ LOG_MODULE_REGISTER(i2c_dw);
#include "i2c-priv.h"
static inline void _i2c_dw_data_ask(struct device *dev)
static inline void i2c_dw_data_ask(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
u32_t data;
@ -96,7 +96,7 @@ static inline void _i2c_dw_data_ask(struct device *dev)
}
}
static void _i2c_dw_data_read(struct device *dev)
static void i2c_dw_data_read(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
@ -123,7 +123,7 @@ static void _i2c_dw_data_read(struct device *dev)
}
static int _i2c_dw_data_send(struct device *dev)
static int i2c_dw_data_send(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
u32_t data = 0U;
@ -168,7 +168,7 @@ static int _i2c_dw_data_send(struct device *dev)
return 0;
}
static inline void _i2c_dw_transfer_complete(struct device *dev)
static inline void i2c_dw_transfer_complete(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
u32_t value;
@ -235,7 +235,7 @@ static void i2c_dw_isr(void *arg)
/* Check if the RX FIFO reached threshold */
if (intr_stat.bits.rx_full) {
_i2c_dw_data_read(port);
i2c_dw_data_read(port);
}
/* Check if the TX FIFO is ready for commands.
@ -245,9 +245,9 @@ static void i2c_dw_isr(void *arg)
if (intr_stat.bits.tx_empty) {
if ((dw->xfr_flags & I2C_MSG_RW_MASK)
== I2C_MSG_WRITE) {
ret = _i2c_dw_data_send(port);
ret = i2c_dw_data_send(port);
} else {
_i2c_dw_data_ask(port);
i2c_dw_data_ask(port);
}
/* If STOP is not expected, finish processing this
@ -270,11 +270,11 @@ static void i2c_dw_isr(void *arg)
return;
done:
_i2c_dw_transfer_complete(port);
i2c_dw_transfer_complete(port);
}
static int _i2c_dw_setup(struct device *dev, u16_t slave_address)
static int i2c_dw_setup(struct device *dev, u16_t slave_address)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
u32_t value;
@ -422,7 +422,7 @@ static int i2c_dw_transfer(struct device *dev,
dw->state |= I2C_DW_BUSY;
ret = _i2c_dw_setup(dev, slave_address);
ret = i2c_dw_setup(dev, slave_address);
if (ret) {
dw->state = I2C_DW_STATE_READY;
return ret;
@ -684,7 +684,7 @@ static int i2c_dw_initialize(struct device *dev)
rom->config_func(dev);
dw->app_config = I2C_MODE_MASTER | _i2c_map_dt_bitrate(rom->bitrate);
dw->app_config = I2C_MODE_MASTER | i2c_map_dt_bitrate(rom->bitrate);
if (i2c_dw_runtime_configure(dev, dw->app_config) != 0) {
LOG_DBG("I2C: Cannot set default configuration");

2
drivers/i2c/i2c_gecko.c
View file

@ -168,7 +168,7 @@ static int i2c_gecko_init(struct device *dev)
i2c_gecko_config_pins(dev, &config->pin_sda, &config->pin_scl);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = i2c_gecko_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (error) {

2
drivers/i2c/i2c_imx.c
View file

@ -335,7 +335,7 @@ static int i2c_imx_init(struct device *dev)
k_sem_init(&data->device_sync_sem, 0, UINT_MAX);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = i2c_imx_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (error) {

2
drivers/i2c/i2c_ll_stm32.c
View file

@ -234,7 +234,7 @@ static int i2c_stm32_init(struct device *dev)
}
#endif /* CONFIG_SOC_SERIES_STM32F3X) || CONFIG_SOC_SERIES_STM32F0X */
bitrate_cfg = _i2c_map_dt_bitrate(cfg->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
ret = i2c_stm32_runtime_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (ret < 0) {

2
drivers/i2c/i2c_ll_stm32_v2.c
View file

@ -195,7 +195,7 @@ int i2c_stm32_slave_register(struct device *dev,
return -EBUSY;
}
bitrate_cfg = _i2c_map_dt_bitrate(cfg->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
if (ret < 0) {

2
drivers/i2c/i2c_mcux.c
View file

@ -181,7 +181,7 @@ static int i2c_mcux_init(struct device *dev)
I2C_MasterTransferCreateHandle(base, &data->handle,
i2c_mcux_master_transfer_callback, dev);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = i2c_mcux_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (error) {

2
drivers/i2c/i2c_mcux_lpi2c.c
View file

@ -197,7 +197,7 @@ static int mcux_lpi2c_init(struct device *dev)
LPI2C_MasterTransferCreateHandle(base, &data->handle,
mcux_lpi2c_master_transfer_callback, dev);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = mcux_lpi2c_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (error) {

8
drivers/i2c/i2c_nrfx_twi.c
View file

@ -175,19 +175,19 @@ static int init_twi(struct device *dev, const nrfx_twi_config_t *config)
return init_twi(dev, &config); \
} \
static struct i2c_nrfx_twi_data twi_##idx##_data = { \
.transfer_sync = _K_SEM_INITIALIZER( \
.transfer_sync = Z_SEM_INITIALIZER( \
twi_##idx##_data.transfer_sync, 1, 1), \
.completion_sync = _K_SEM_INITIALIZER( \
.completion_sync = Z_SEM_INITIALIZER( \
twi_##idx##_data.completion_sync, 0, 1) \
}; \
static const struct i2c_nrfx_twi_config twi_##idx##_config = { \
static const struct i2c_nrfx_twi_config twi_##idx##z_config = { \
.twi = NRFX_TWI_INSTANCE(idx) \
}; \
DEVICE_AND_API_INIT(twi_##idx, \
DT_NORDIC_NRF_I2C_I2C_##idx##_LABEL, \
twi_##idx##_init, \
&twi_##idx##_data, \
&twi_##idx##_config, \
&twi_##idx##z_config, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_nrfx_twi_driver_api)

8
drivers/i2c/i2c_nrfx_twim.c
View file

@ -178,19 +178,19 @@ static int init_twim(struct device *dev, const nrfx_twim_config_t *config)
return init_twim(dev, &config); \
} \
static struct i2c_nrfx_twim_data twim_##idx##_data = { \
.transfer_sync = _K_SEM_INITIALIZER( \
.transfer_sync = Z_SEM_INITIALIZER( \
twim_##idx##_data.transfer_sync, 1, 1), \
.completion_sync = _K_SEM_INITIALIZER( \
.completion_sync = Z_SEM_INITIALIZER( \
twim_##idx##_data.completion_sync, 0, 1) \
}; \
static const struct i2c_nrfx_twim_config twim_##idx##_config = { \
static const struct i2c_nrfx_twim_config twim_##idx##z_config = { \
.twim = NRFX_TWIM_INSTANCE(idx) \
}; \
DEVICE_AND_API_INIT(twim_##idx, \
DT_NORDIC_NRF_I2C_I2C_##idx##_LABEL, \
twim_##idx##_init, \
&twim_##idx##_data, \
&twim_##idx##_config, \
&twim_##idx##z_config, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_nrfx_twim_driver_api)

2
drivers/i2c/i2c_qmsi.c
View file

@ -313,7 +313,7 @@ static int i2c_qmsi_init(struct device *dev)
clk_periph_enable(config->clock_gate);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
err = i2c_qmsi_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (err < 0) {

2
drivers/i2c/i2c_qmsi_ss.c
View file

@ -363,7 +363,7 @@ static int i2c_qmsi_ss_init(struct device *dev)
k_sem_init(&driver_data->sem, 1, UINT_MAX);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
err = i2c_qmsi_ss_configure(dev, I2C_MODE_MASTER | bitrate_cfg);

2
drivers/i2c/i2c_sam_twi.c
View file

@ -315,7 +315,7 @@ static int i2c_sam_twi_initialize(struct device *dev)
/* Reset TWI module */
twi->TWI_CR = TWI_CR_SWRST;
bitrate_cfg = _i2c_map_dt_bitrate(dev_cfg->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(dev_cfg->bitrate);
ret = i2c_sam_twi_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (ret < 0) {

2
drivers/i2c/i2c_sam_twihs.c
View file

@ -302,7 +302,7 @@ static int i2c_sam_twihs_initialize(struct device *dev)
/* Reset the module */
twihs->TWIHS_CR = TWIHS_CR_SWRST;
bitrate_cfg = _i2c_map_dt_bitrate(dev_cfg->bitrate);
bitrate_cfg = i2c_map_dt_bitrate(dev_cfg->bitrate);
ret = i2c_sam_twihs_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (ret < 0) {

2
drivers/i2c/i2c_sifive.c
View file

@ -311,7 +311,7 @@ static int i2c_sifive_init(struct device *dev)
u32_t dev_config = 0U;
int rc = 0;
dev_config = (I2C_MODE_MASTER | _i2c_map_dt_bitrate(config->f_bus));
dev_config = (I2C_MODE_MASTER | i2c_map_dt_bitrate(config->f_bus));
rc = i2c_sifive_configure(dev, dev_config);
if (rc != 0) {

4
drivers/i2s/i2s_ll_stm32.c
View file

@ -110,8 +110,8 @@ static int i2s_stm32_enable_clock(struct device *dev)
#define PLLI2S_MAX_MS_TIME 1 /* PLLI2S lock time is 300us max */
static u16_t plli2s_ms_count;
#define _pllr(v) LL_RCC_PLLI2SR_DIV_ ## v
#define pllr(v) _pllr(v)
#define z_pllr(v) LL_RCC_PLLI2SR_DIV_ ## v
#define pllr(v) z_pllr(v)
#endif
static int i2s_stm32_set_clock(struct device *dev, u32_t bit_clk_freq)

24
drivers/ieee802154/ieee802154_cc1200.c
View file

@ -50,7 +50,7 @@ static struct spi_cs_control cs_ctrl;
/***********************
* Debugging functions *
**********************/
static void _cc1200_print_status(u8_t status)
static void cc1200_print_status(u8_t status)
{
if (status == CC1200_STATUS_IDLE) {
LOG_DBG("Idling");
@ -75,7 +75,7 @@ static void _cc1200_print_status(u8_t status)
* Generic functions *
********************/
bool _cc1200_access_reg(struct cc1200_context *ctx, bool read, u8_t addr,
bool z_cc1200_access_reg(struct cc1200_context *ctx, bool read, u8_t addr,
void *data, size_t length, bool extended, bool burst)
{
u8_t cmd_buf[2];
@ -160,7 +160,7 @@ static u8_t get_status(struct cc1200_context *ctx)
{
u8_t val;
if (_cc1200_access_reg(ctx, true, CC1200_INS_SNOP,
if (z_cc1200_access_reg(ctx, true, CC1200_INS_SNOP,
&val, 1, false, false)) {
/* See Section 3.1.2 */
return val & CC1200_STATUS_MASK;
@ -239,7 +239,7 @@ static bool write_reg_freq(struct cc1200_context *ctx, u32_t freq)
freq_data[1] = (u8_t)((freq & 0x0000FF00) >> 8);
freq_data[2] = (u8_t)(freq & 0x000000FF);
return _cc1200_access_reg(ctx, false, CC1200_REG_FREQ2,
return z_cc1200_access_reg(ctx, false, CC1200_REG_FREQ2,
freq_data, 3, true, true);
}
@ -329,10 +329,10 @@ rf_install_settings(struct device *dev,
{
struct cc1200_context *cc1200 = dev->driver_data;
if (!_cc1200_access_reg(cc1200, false, CC1200_REG_SYNC3,
if (!z_cc1200_access_reg(cc1200, false, CC1200_REG_SYNC3,
(void *)rf_settings->registers,
CC1200_RF_NON_EXT_SPACE_REGS, false, true) ||
!_cc1200_access_reg(cc1200, false, CC1200_REG_IF_MIX_CFG,
!z_cc1200_access_reg(cc1200, false, CC1200_REG_IF_MIX_CFG,
(void *)rf_settings->registers +
CC1200_RF_NON_EXT_SPACE_REGS,
CC1200_RF_EXT_SPACE_REGS, true, true) ||
@ -365,7 +365,7 @@ static int rf_calibrate(struct cc1200_context *ctx)
k_busy_wait(USEC_PER_MSEC * 10U);
_cc1200_print_status(get_status(ctx));
cc1200_print_status(get_status(ctx));
return 0;
}
@ -377,7 +377,7 @@ static int rf_calibrate(struct cc1200_context *ctx)
static inline bool write_txfifo(struct cc1200_context *ctx,
void *data, size_t length)
{
return _cc1200_access_reg(ctx, false,
return z_cc1200_access_reg(ctx, false,
CC1200_REG_TXFIFO,
data, length, false, true);
}
@ -389,7 +389,7 @@ static inline bool write_txfifo(struct cc1200_context *ctx,
static inline bool read_rxfifo(struct cc1200_context *ctx,
void *data, size_t length)
{
return _cc1200_access_reg(ctx, true,
return z_cc1200_access_reg(ctx, true,
CC1200_REG_RXFIFO,
data, length, false, true);
}
@ -398,7 +398,7 @@ static inline u8_t get_packet_length(struct cc1200_context *ctx)
{
u8_t len;
if (_cc1200_access_reg(ctx, true, CC1200_REG_RXFIFO,
if (z_cc1200_access_reg(ctx, true, CC1200_REG_RXFIFO,
&len, 1, false, true)) {
return len;
}
@ -642,7 +642,7 @@ static int cc1200_tx(struct device *dev,
}
out:
_cc1200_print_status(get_status(cc1200));
cc1200_print_status(get_status(cc1200));
if (atomic_get(&cc1200->tx) == 1 &&
read_reg_num_txbytes(cc1200) != 0) {
@ -677,7 +677,7 @@ static int cc1200_start(struct device *dev)
enable_gpio0_interrupt(cc1200, true);
_cc1200_print_status(get_status(cc1200));
cc1200_print_status(get_status(cc1200));
return 0;
}

20
drivers/ieee802154/ieee802154_cc1200.h
View file

@ -47,43 +47,43 @@ struct cc1200_context {
***************************
*/
bool _cc1200_access_reg(struct cc1200_context *ctx, bool read, u8_t addr,
bool z_cc1200_access_reg(struct cc1200_context *ctx, bool read, u8_t addr,
void *data, size_t length, bool extended, bool burst);
static inline u8_t _cc1200_read_single_reg(struct cc1200_context *ctx,
static inline u8_t cc1200_read_single_reg(struct cc1200_context *ctx,
u8_t addr, bool extended)
{
u8_t val;
if (_cc1200_access_reg(ctx, true, addr, &val, 1, extended, false)) {
if (z_cc1200_access_reg(ctx, true, addr, &val, 1, extended, false)) {
return val;
}
return 0;
}
static inline bool _cc1200_write_single_reg(struct cc1200_context *ctx,
static inline bool cc1200_write_single_reg(struct cc1200_context *ctx,
u8_t addr, u8_t val, bool extended)
{
return _cc1200_access_reg(ctx, false, addr, &val, 1, extended, false);
return z_cc1200_access_reg(ctx, false, addr, &val, 1, extended, false);
}
static inline bool _cc1200_instruct(struct cc1200_context *ctx, u8_t addr)
static inline bool cc1200_instruct(struct cc1200_context *ctx, u8_t addr)
{
return _cc1200_access_reg(ctx, false, addr, NULL, 0, false, false);
return z_cc1200_access_reg(ctx, false, addr, NULL, 0, false, false);
}
#define DEFINE_REG_READ(__reg_name, __reg_addr, __ext) \
static inline u8_t read_reg_##__reg_name(struct cc1200_context *ctx) \
{ \
return _cc1200_read_single_reg(ctx, __reg_addr, __ext); \
return cc1200_read_single_reg(ctx, __reg_addr, __ext); \
}
#define DEFINE_REG_WRITE(__reg_name, __reg_addr, __ext) \
static inline bool write_reg_##__reg_name(struct cc1200_context *ctx, \
u8_t val) \
{ \
return _cc1200_write_single_reg(ctx, __reg_addr, \
return cc1200_write_single_reg(ctx, __reg_addr, \
val, __ext); \
}
@ -107,7 +107,7 @@ DEFINE_REG_READ(num_rxbytes, CC1200_REG_NUM_RXBYTES, true)
#define DEFINE_STROBE_INSTRUCTION(__ins_name, __ins_addr) \
static inline bool instruct_##__ins_name(struct cc1200_context *ctx) \
{ \
return _cc1200_instruct(ctx, __ins_addr); \
return cc1200_instruct(ctx, __ins_addr); \
}
DEFINE_STROBE_INSTRUCTION(sres, CC1200_INS_SRES)

92
drivers/ieee802154/ieee802154_cc2520.c
View file

@ -64,7 +64,7 @@ static struct spi_cs_control cs_ctrl;
* DEBUG *
********/
#if LOG_LEVEL == LOG_LEVEL_DBG
static inline void _cc2520_print_gpio_config(struct device *dev)
static inline void cc2520_print_gpio_config(struct device *dev)
{
struct cc2520_context *cc2520 = dev->driver_data;
@ -81,7 +81,7 @@ static inline void _cc2520_print_gpio_config(struct device *dev)
read_reg_gpioctrl(cc2520));
}
static inline void _cc2520_print_exceptions(struct cc2520_context *cc2520)
static inline void cc2520_print_exceptions(struct cc2520_context *cc2520)
{
u8_t flag = read_reg_excflag0(cc2520);
@ -156,7 +156,7 @@ static inline void _cc2520_print_exceptions(struct cc2520_context *cc2520)
}
}
static inline void _cc2520_print_errors(struct cc2520_context *cc2520)
static inline void cc2520_print_errors(struct cc2520_context *cc2520)
{
u8_t flag = read_reg_excflag2(cc2520);
@ -191,18 +191,18 @@ static inline void _cc2520_print_errors(struct cc2520_context *cc2520)
}
}
#else
#define _cc2520_print_gpio_config(...)
#define _cc2520_print_exceptions(...)
#define _cc2520_print_errors(...)
#define cc2520_print_gpio_config(...)
#define cc2520_print_exceptions(...)
#define cc2520_print_errors(...)
#endif /* LOG_LEVEL == LOG_LEVEL_DBG */
/*********************
* Generic functions *
********************/
#define _usleep(usec) k_busy_wait(usec)
#define z_usleep(usec) k_busy_wait(usec)
bool _cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
bool z_cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
u16_t addr, void *data, size_t length)
{
u8_t cmd_buf[2];
@ -248,11 +248,11 @@ bool _cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
return (spi_write(ctx->spi, &ctx->spi_cfg, &tx) == 0);
}
static inline u8_t _cc2520_status(struct cc2520_context *ctx)
static inline u8_t cc2520_status(struct cc2520_context *ctx)
{
u8_t status;
if (_cc2520_access(ctx, true, CC2520_INS_SNOP, 0, &status, 1)) {
if (z_cc2520_access(ctx, true, CC2520_INS_SNOP, 0, &status, 1)) {
return status;
}
@ -265,8 +265,8 @@ static bool verify_osc_stabilization(struct cc2520_context *cc2520)
u8_t status;
do {
status = _cc2520_status(cc2520);
_usleep(1);
status = cc2520_status(cc2520);
z_usleep(1);
timeout--;
} while (!(status & CC2520_STATUS_XOSC_STABLE_N_RUNNING) && timeout);
@ -299,7 +299,7 @@ static inline u8_t *get_mac(struct device *dev)
return cc2520->mac_addr;
}
static int _cc2520_set_pan_id(struct device *dev, u16_t pan_id)
static int cc2520_set_pan_id(struct device *dev, u16_t pan_id)
{
struct cc2520_context *cc2520 = dev->driver_data;
@ -315,7 +315,7 @@ static int _cc2520_set_pan_id(struct device *dev, u16_t pan_id)
return 0;
}
static int _cc2520_set_short_addr(struct device *dev, u16_t short_addr)
static int cc2520_set_short_addr(struct device *dev, u16_t short_addr)
{
struct cc2520_context *cc2520 = dev->driver_data;
@ -331,7 +331,7 @@ static int _cc2520_set_short_addr(struct device *dev, u16_t short_addr)
return 0;
}
static int _cc2520_set_ieee_addr(struct device *dev, const u8_t *ieee_addr)
static int cc2520_set_ieee_addr(struct device *dev, const u8_t *ieee_addr)
{
struct cc2520_context *cc2520 = dev->driver_data;
@ -477,13 +477,13 @@ static inline bool write_txfifo_length(struct cc2520_context *ctx, u8_t len)
{
u8_t length = len + CC2520_FCS_LENGTH;
return _cc2520_access(ctx, false, CC2520_INS_TXBUF, 0, &length, 1);
return z_cc2520_access(ctx, false, CC2520_INS_TXBUF, 0, &length, 1);
}
static inline bool write_txfifo_content(struct cc2520_context *ctx,
u8_t *frame, u8_t len)
{
return _cc2520_access(ctx, false, CC2520_INS_TXBUF, 0, frame, len);
return z_cc2520_access(ctx, false, CC2520_INS_TXBUF, 0, frame, len);
}
static inline bool verify_txfifo_status(struct cc2520_context *cc2520,
@ -503,7 +503,7 @@ static inline bool verify_tx_done(struct cc2520_context *cc2520)
u8_t status;
do {
_usleep(1);
z_usleep(1);
timeout--;
status = read_reg_excflag0(cc2520);
} while (!(status & EXCFLAG0_TX_FRM_DONE) && timeout);
@ -533,7 +533,7 @@ static inline u8_t read_rxfifo_length(struct cc2520_context *ctx)
u8_t len;
if (_cc2520_access(ctx, true, CC2520_INS_RXBUF, 0, &len, 1)) {
if (z_cc2520_access(ctx, true, CC2520_INS_RXBUF, 0, &len, 1)) {
return len;
}
@ -543,7 +543,7 @@ static inline u8_t read_rxfifo_length(struct cc2520_context *ctx)
static inline bool read_rxfifo_content(struct cc2520_context *ctx,
struct net_buf *buf, u8_t len)
{
if (!_cc2520_access(ctx, true, CC2520_INS_RXBUF, 0, buf->data, len)) {
if (!z_cc2520_access(ctx, true, CC2520_INS_RXBUF, 0, buf->data, len)) {
return false;
}
@ -589,7 +589,7 @@ static inline bool verify_crc(struct cc2520_context *ctx, struct net_pkt *pkt)
{
u8_t fcs[2];
if (!_cc2520_access(ctx, true, CC2520_INS_RXBUF, 0, &fcs, 2)) {
if (!z_cc2520_access(ctx, true, CC2520_INS_RXBUF, 0, &fcs, 2)) {
return false;
}
@ -675,8 +675,8 @@ static void cc2520_rx(int arg)
K_THREAD_STACK_SIZEOF(cc2520->cc2520_rx_stack));
continue;
flush:
_cc2520_print_exceptions(cc2520);
_cc2520_print_errors(cc2520);
cc2520_print_exceptions(cc2520);
cc2520_print_errors(cc2520);
flush_rxfifo(cc2520);
out:
if (pkt) {
@ -741,11 +741,11 @@ static int cc2520_filter(struct device *dev,
}
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
return _cc2520_set_ieee_addr(dev, filter->ieee_addr);
return cc2520_set_ieee_addr(dev, filter->ieee_addr);
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
return _cc2520_set_short_addr(dev, filter->short_addr);
return cc2520_set_short_addr(dev, filter->short_addr);
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
return _cc2520_set_pan_id(dev, filter->pan_id);
return cc2520_set_pan_id(dev, filter->pan_id);
}
return -ENOTSUP;
@ -858,8 +858,8 @@ error:
k_sem_give(&cc2520->access_lock);
#endif
LOG_ERR("No TX_FRM_DONE");
_cc2520_print_exceptions(cc2520);
_cc2520_print_errors(cc2520);
cc2520_print_exceptions(cc2520);
cc2520_print_errors(cc2520);
atomic_set(&cc2520->tx, 0);
instruct_sflushtx(cc2520);
@ -913,17 +913,17 @@ static int power_on_and_setup(struct device *dev)
/* Switching to LPM2 mode */
set_reset(dev, 0);
_usleep(150);
z_usleep(150);
set_vreg_en(dev, 0);
_usleep(250);
z_usleep(250);
/* Then to ACTIVE mode */
set_vreg_en(dev, 1);
_usleep(250);
z_usleep(250);
set_reset(dev, 1);
_usleep(150);
z_usleep(150);
if (!verify_osc_stabilization(cc2520)) {
return -EIO;
@ -968,7 +968,7 @@ static int power_on_and_setup(struct device *dev)
setup_gpio_callbacks(dev);
_cc2520_print_gpio_config(dev);
cc2520_print_gpio_config(dev);
return 0;
}
@ -1097,17 +1097,17 @@ NET_STACK_INFO_ADDR(RX, cc2520,
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
static inline bool _cc2520_read_ram(struct cc2520_context *ctx, u16_t addr,
static inline bool cc2520_read_ram(struct cc2520_context *ctx, u16_t addr,
u8_t *data_buf, u8_t len)
{
return _cc2520_access(ctx, true, CC2520_INS_MEMRD,
return z_cc2520_access(ctx, true, CC2520_INS_MEMRD,
addr, data_buf, len);
}
static inline bool _cc2520_write_ram(struct cc2520_context *ctx, u16_t addr,
static inline bool cc2520_write_ram(struct cc2520_context *ctx, u16_t addr,
u8_t *data_buf, u8_t len)
{
return _cc2520_access(ctx, false, CC2520_INS_MEMWR,
return z_cc2520_access(ctx, false, CC2520_INS_MEMWR,
addr, data_buf, len);
}
@ -1245,7 +1245,7 @@ static int insert_crypto_parameters(struct cipher_ctx *ctx,
}
/* Writing the frame in RAM */
if (!_cc2520_write_ram(cc2520, CC2520_MEM_DATA, in_buf, in_len)) {
if (!cc2520_write_ram(cc2520, CC2520_MEM_DATA, in_buf, in_len)) {
LOG_ERR("Cannot write the frame in RAM");
return -EIO;
}
@ -1254,7 +1254,7 @@ static int insert_crypto_parameters(struct cipher_ctx *ctx,
sys_memcpy_swap(data, ctx->key.bit_stream, ctx->keylen);
/* Writing the key in RAM */
if (!_cc2520_write_ram(cc2520, CC2520_MEM_KEY, data, 16)) {
if (!cc2520_write_ram(cc2520, CC2520_MEM_KEY, data, 16)) {
LOG_ERR("Cannot write the key in RAM");
return -EIO;
}
@ -1262,7 +1262,7 @@ static int insert_crypto_parameters(struct cipher_ctx *ctx,
generate_nonce(ccm_nonce, data, apkt, m);
/* Writing the nonce in RAM */
if (!_cc2520_write_ram(cc2520, CC2520_MEM_NONCE, data, 16)) {
if (!cc2520_write_ram(cc2520, CC2520_MEM_NONCE, data, 16)) {
LOG_ERR("Cannot write the nonce in RAM");
return -EIO;
}
@ -1270,7 +1270,7 @@ static int insert_crypto_parameters(struct cipher_ctx *ctx,
return m;
}
static int _cc2520_crypto_ccm(struct cipher_ctx *ctx,
static int cc2520_crypto_ccm(struct cipher_ctx *ctx,
struct cipher_aead_pkt *apkt,
u8_t *ccm_nonce)
{
@ -1301,7 +1301,7 @@ static int _cc2520_crypto_ccm(struct cipher_ctx *ctx,
if (!instruct_uccm_ccm(cc2520, false, CC2520_MEM_KEY >> 4, auth_crypt,
CC2520_MEM_NONCE >> 4, CC2520_MEM_DATA,
0x000, apkt->ad_len, m) ||
!_cc2520_read_ram(cc2520, CC2520_MEM_DATA,
!cc2520_read_ram(cc2520, CC2520_MEM_DATA,
apkt->pkt->out_buf, apkt->pkt->out_len)) {
LOG_ERR("CCM or reading result from RAM failed");
return -EIO;
@ -1315,7 +1315,7 @@ static int _cc2520_crypto_ccm(struct cipher_ctx *ctx,
return 0;
}
static int _cc2520_crypto_uccm(struct cipher_ctx *ctx,
static int cc2520_crypto_uccm(struct cipher_ctx *ctx,
struct cipher_aead_pkt *apkt,
u8_t *ccm_nonce)
{
@ -1343,7 +1343,7 @@ static int _cc2520_crypto_uccm(struct cipher_ctx *ctx,
if (!instruct_uccm_ccm(cc2520, true, CC2520_MEM_KEY >> 4, auth_crypt,
CC2520_MEM_NONCE >> 4, CC2520_MEM_DATA,
0x000, apkt->ad_len, m) ||
!_cc2520_read_ram(cc2520, CC2520_MEM_DATA,
!cc2520_read_ram(cc2520, CC2520_MEM_DATA,
apkt->pkt->out_buf, apkt->pkt->out_len)) {
LOG_ERR("UCCM or reading result from RAM failed");
return -EIO;
@ -1380,9 +1380,9 @@ static int cc2520_crypto_begin_session(struct device *dev,
}
if (op_type == CRYPTO_CIPHER_OP_ENCRYPT) {
ctx->ops.ccm_crypt_hndlr = _cc2520_crypto_ccm;
ctx->ops.ccm_crypt_hndlr = cc2520_crypto_ccm;
} else {
ctx->ops.ccm_crypt_hndlr = _cc2520_crypto_uccm;
ctx->ops.ccm_crypt_hndlr = cc2520_crypto_uccm;
}
ctx->ops.cipher_mode = mode;

24
drivers/ieee802154/ieee802154_cc2520.h
View file

@ -48,7 +48,7 @@ struct cc2520_context {
***************************
*/
bool _cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
bool z_cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
u16_t addr, void *data, size_t length);
#define DEFINE_SREG_READ(__reg_name, __reg_addr) \
@ -56,7 +56,7 @@ bool _cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
{ \
u8_t val; \
\
if (_cc2520_access(ctx, true, CC2520_INS_MEMRD, \
if (z_cc2520_access(ctx, true, CC2520_INS_MEMRD, \
__reg_addr, &val, 1)) { \
return val; \
} \
@ -68,7 +68,7 @@ bool _cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
static inline bool write_reg_##__reg_name(struct cc2520_context *ctx, \
u8_t val) \
{ \
return _cc2520_access(ctx, false, CC2520_INS_MEMWR, \
return z_cc2520_access(ctx, false, CC2520_INS_MEMWR, \
__reg_addr, &val, 1); \
}
@ -77,7 +77,7 @@ bool _cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
{ \
u8_t val; \
\
if (_cc2520_access(ctx, true, CC2520_INS_REGRD, \
if (z_cc2520_access(ctx, true, CC2520_INS_REGRD, \
__reg_addr, &val, 1)) { \
return val; \
} \
@ -89,7 +89,7 @@ bool _cc2520_access(struct cc2520_context *ctx, bool read, u8_t ins,
static inline bool write_reg_##__reg_name(struct cc2520_context *ctx, \
u8_t val) \
{ \
return _cc2520_access(ctx, false, CC2520_INS_REGWR, \
return z_cc2520_access(ctx, false, CC2520_INS_REGWR, \
__reg_addr, &val, 1); \
}
@ -140,7 +140,7 @@ DEFINE_SREG_WRITE(extclock, CC2520_SREG_EXTCLOCK)
static inline bool write_mem_##__mem_name(struct cc2520_context *ctx, \
u8_t *buf) \
{ \
return _cc2520_access(ctx, false, CC2520_INS_MEMWR, \
return z_cc2520_access(ctx, false, CC2520_INS_MEMWR, \
__addr, buf, __sz); \
}
@ -153,30 +153,30 @@ DEFINE_MEM_WRITE(ext_addr, CC2520_MEM_EXT_ADDR, 8)
******************************
*/
static inline bool _cc2520_command_strobe(struct cc2520_context *ctx,
static inline bool cc2520_command_strobe(struct cc2520_context *ctx,
u8_t instruction)
{
return _cc2520_access(ctx, false, instruction, 0, NULL, 0);
return z_cc2520_access(ctx, false, instruction, 0, NULL, 0);
}
static inline bool _cc2520_command_strobe_snop(struct cc2520_context *ctx,
static inline bool cc2520_command_strobe_snop(struct cc2520_context *ctx,
u8_t instruction)
{
u8_t snop[1] = { CC2520_INS_SNOP };
return _cc2520_access(ctx, false, instruction, 0, snop, 1);
return z_cc2520_access(ctx, false, instruction, 0, snop, 1);
}
#define DEFINE_STROBE_INSTRUCTION(__ins_name, __ins) \
static inline bool instruct_##__ins_name(struct cc2520_context *ctx) \
{ \
return _cc2520_command_strobe(ctx, __ins); \
return cc2520_command_strobe(ctx, __ins); \
}
#define DEFINE_STROBE_SNOP_INSTRUCTION(__ins_name, __ins) \
static inline bool instruct_##__ins_name(struct cc2520_context *ctx) \
{ \
return _cc2520_command_strobe_snop(ctx, __ins); \
return cc2520_command_strobe_snop(ctx, __ins); \
}
DEFINE_STROBE_INSTRUCTION(srxon, CC2520_INS_SRXON)

32
drivers/ieee802154/ieee802154_mcr20a.c
View file

@ -145,10 +145,10 @@ static const u16_t pll_frac_lt[16] = {
2048, 12288, 22528, 32768
};
#define _usleep(usec) k_busy_wait(usec)
#define z_usleep(usec) k_busy_wait(usec)
/* Read direct (dreg is true) or indirect register (dreg is false) */
u8_t _mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, u8_t addr)
u8_t z_mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, u8_t addr)
{
u8_t cmd_buf[3] = {
dreg ? (MCR20A_REG_READ | addr) :
@ -180,7 +180,7 @@ u8_t _mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, u8_t addr)
}
/* Write direct (dreg is true) or indirect register (dreg is false) */
bool _mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, u8_t addr,
bool z_mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, u8_t addr,
u8_t value)
{
u8_t cmd_buf[3] = {
@ -202,7 +202,7 @@ bool _mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, u8_t addr,
}
/* Write multiple bytes to direct or indirect register */
bool _mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
bool z_mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
u8_t *data_buf, u8_t len)
{
u8_t cmd_buf[2] = {
@ -229,7 +229,7 @@ bool _mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
}
/* Read multiple bytes from direct or indirect register */
bool _mcr20a_read_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
bool z_mcr20a_read_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
u8_t *data_buf, u8_t len)
{
u8_t cmd_buf[2] = {
@ -405,7 +405,7 @@ error:
return -EIO;
}
static inline void _xcvseq_wait_until_idle(struct mcr20a_context *mcr20a)
static inline void xcvseq_wait_until_idle(struct mcr20a_context *mcr20a)
{
u8_t state;
u8_t retries = MCR20A_GET_SEQ_STATE_RETRIES;
@ -441,7 +441,7 @@ static inline int mcr20a_abort_sequence(struct mcr20a_context *mcr20a,
return -1;
}
_xcvseq_wait_until_idle(mcr20a);
xcvseq_wait_until_idle(mcr20a);
/* Clear relevant interrupt flags */
if (!write_reg_irqsts1(mcr20a, MCR20A_IRQSTS1_IRQ_MASK)) {
@ -594,7 +594,7 @@ out:
* if a new sequence is to be set. This function is only to be called
* when a sequence has been completed.
*/
static inline bool _irqsts1_event(struct mcr20a_context *mcr20a,
static inline bool irqsts1_event(struct mcr20a_context *mcr20a,
u8_t *dregs)
{
u8_t seq = dregs[MCR20A_PHY_CTRL1] & MCR20A_PHY_CTRL1_XCVSEQ_MASK;
@ -681,7 +681,7 @@ static inline bool _irqsts1_event(struct mcr20a_context *mcr20a,
* Currently we use only T4CMP to cancel the running sequence,
* usually the TR.
*/
static inline bool _irqsts3_event(struct mcr20a_context *mcr20a,
static inline bool irqsts3_event(struct mcr20a_context *mcr20a,
u8_t *dregs)
{
bool retval = false;
@ -736,9 +736,9 @@ static void mcr20a_thread_main(void *arg)
ctrl1 = dregs[MCR20A_PHY_CTRL1];
if (dregs[MCR20A_IRQSTS3] & MCR20A_IRQSTS3_IRQ_MASK) {
set_new_seq = _irqsts3_event(mcr20a, dregs);
set_new_seq = irqsts3_event(mcr20a, dregs);
} else if (dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_SEQIRQ) {
set_new_seq = _irqsts1_event(mcr20a, dregs);
set_new_seq = irqsts1_event(mcr20a, dregs);
}
if (dregs[MCR20A_IRQSTS2] & MCR20A_IRQSTS2_IRQ_MASK) {
@ -759,7 +759,7 @@ static void mcr20a_thread_main(void *arg)
LOG_ERR("Failed to reset SEQ manager");
}
_xcvseq_wait_until_idle(mcr20a);
xcvseq_wait_until_idle(mcr20a);
if (!write_burst_irqsts1_ctrl1(mcr20a, dregs)) {
LOG_ERR("Failed to write CTRL1");
@ -1158,7 +1158,7 @@ static int mcr20a_start(struct device *dev)
}
do {
_usleep(50);
z_usleep(50);
timeout--;
status = read_reg_pwr_modes(mcr20a);
} while (!(status & MCR20A_PWR_MODES_XTAL_READY) && timeout);
@ -1251,7 +1251,7 @@ static int mcr20a_update_overwrites(struct mcr20a_context *dev)
i < sizeof(overwrites_indirect) / sizeof(overwrites_t);
i++) {
if (!_mcr20a_write_reg(dev, false,
if (!z_mcr20a_write_reg(dev, false,
overwrites_indirect[i].address,
overwrites_indirect[i].data)) {
goto error;
@ -1274,11 +1274,11 @@ static int power_on_and_setup(struct device *dev)
if (!PART_OF_KW2XD_SIP) {
set_reset(dev, 0);
_usleep(150);
z_usleep(150);
set_reset(dev, 1);
do {
_usleep(50);
z_usleep(50);
timeout--;
gpio_pin_read(mcr20a->irq_gpio,
DT_NXP_MCR20A_0_IRQB_GPIOS_PIN, &status);

16
drivers/ieee802154/ieee802154_mcr20a.h
View file

@ -42,25 +42,25 @@ struct mcr20a_context {
#include "ieee802154_mcr20a_regs.h"
u8_t _mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, u8_t addr);
bool _mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, u8_t addr,
u8_t z_mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, u8_t addr);
bool z_mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, u8_t addr,
u8_t value);
bool _mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
bool z_mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
u8_t *data_buf, u8_t len);
bool _mcr20a_read_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
bool z_mcr20a_read_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
u8_t *data_buf, u8_t len);
#define DEFINE_REG_READ(__reg_name, __reg_addr, __dreg) \
static inline u8_t read_reg_##__reg_name(struct mcr20a_context *dev) \
{ \
return _mcr20a_read_reg(dev, __dreg, __reg_addr); \
return z_mcr20a_read_reg(dev, __dreg, __reg_addr); \
}
#define DEFINE_REG_WRITE(__reg_name, __reg_addr, __dreg) \
static inline bool write_reg_##__reg_name(struct mcr20a_context *dev, \
u8_t value) \
{ \
return _mcr20a_write_reg(dev, __dreg, __reg_addr, value); \
return z_mcr20a_write_reg(dev, __dreg, __reg_addr, value); \
}
#define DEFINE_DREG_READ(__reg_name, __reg_addr) \
@ -153,14 +153,14 @@ DEFINE_BITS_SET(clk_out_div, MCR20A_CLK_OUT, _DIV)
static inline bool write_burst_##__reg_addr( \
struct mcr20a_context *dev, u8_t *buf) \
{ \
return _mcr20a_write_burst(dev, __dreg, __addr, buf, __sz); \
return z_mcr20a_write_burst(dev, __dreg, __addr, buf, __sz); \
}
#define DEFINE_BURST_READ(__reg_addr, __addr, __sz, __dreg) \
static inline bool read_burst_##__reg_addr(struct mcr20a_context *dev, \
u8_t *buf) \
{ \
return _mcr20a_read_burst(dev, __dreg, __addr, buf, __sz); \
return z_mcr20a_read_burst(dev, __dreg, __addr, buf, __sz); \
}
DEFINE_BURST_WRITE(t1cmp, MCR20A_T1CMP_LSB, 3, true)

24
drivers/interrupt_controller/arcv2_irq_unit.c
View file

@ -61,7 +61,7 @@ static struct arc_v2_irq_unit_ctx ctx;
* @return N/A
*/
static int _arc_v2_irq_unit_init(struct device *unused)
static int arc_v2_irq_unit_init(struct device *unused)
{
ARG_UNUSED(unused);
int irq; /* the interrupt index */
@ -107,7 +107,7 @@ unsigned int z_arc_v2_irq_unit_trigger_get(int irq)
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static int _arc_v2_irq_unit_suspend(struct device *dev)
static int arc_v2_irq_unit_suspend(struct device *dev)
{
u8_t irq;
@ -135,7 +135,7 @@ static int _arc_v2_irq_unit_suspend(struct device *dev)
return 0;
}
static int _arc_v2_irq_unit_resume(struct device *dev)
static int arc_v2_irq_unit_resume(struct device *dev)
{
u8_t irq;
u32_t status32;
@ -166,7 +166,7 @@ static int _arc_v2_irq_unit_resume(struct device *dev)
z_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE, ctx.irq_vect_base);
status32 = z_arc_v2_aux_reg_read(_ARC_V2_STATUS32);
status32 |= _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
status32 |= Z_ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
__builtin_arc_kflag(status32);
@ -175,7 +175,7 @@ static int _arc_v2_irq_unit_resume(struct device *dev)
return 0;
}
static int _arc_v2_irq_unit_get_state(struct device *dev)
static int arc_v2_irq_unit_get_state(struct device *dev)
{
ARG_UNUSED(dev);
@ -186,19 +186,19 @@ static int _arc_v2_irq_unit_get_state(struct device *dev)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int _arc_v2_irq_unit_device_ctrl(struct device *device,
static int arc_v2_irq_unit_device_ctrl(struct device *device,
u32_t ctrl_command, void *context, device_pm_cb cb, void *arg)
{
int ret = 0;
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
ret = _arc_v2_irq_unit_suspend(device);
ret = arc_v2_irq_unit_suspend(device);
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
ret = _arc_v2_irq_unit_resume(device);
ret = arc_v2_irq_unit_resume(device);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((u32_t *)context) = _arc_v2_irq_unit_get_state(device);
*((u32_t *)context) = arc_v2_irq_unit_get_state(device);
}
if (cb) {
@ -208,10 +208,10 @@ static int _arc_v2_irq_unit_device_ctrl(struct device *device,
return ret;
}
SYS_DEVICE_DEFINE("arc_v2_irq_unit", _arc_v2_irq_unit_init,
_arc_v2_irq_unit_device_ctrl, PRE_KERNEL_1,
SYS_DEVICE_DEFINE("arc_v2_irq_unit", arc_v2_irq_unit_init,
arc_v2_irq_unit_device_ctrl, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#else
SYS_INIT(_arc_v2_irq_unit_init, PRE_KERNEL_1,
SYS_INIT(arc_v2_irq_unit_init, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */

10
drivers/interrupt_controller/ioapic_intr.c
View file

@ -80,7 +80,7 @@ static void __IoApicSet(s32_t offset, u32_t value);
static void ioApicRedSetHi(unsigned int irq, u32_t upper32);
static void ioApicRedSetLo(unsigned int irq, u32_t lower32);
static u32_t ioApicRedGetLo(unsigned int irq);
static void _IoApicRedUpdateLo(unsigned int irq, u32_t value,
static void IoApicRedUpdateLo(unsigned int irq, u32_t value,
u32_t mask);
/*
@ -135,7 +135,7 @@ int _ioapic_init(struct device *unused)
*/
void z_ioapic_irq_enable(unsigned int irq)
{
_IoApicRedUpdateLo(irq, 0, IOAPIC_INT_MASK);
IoApicRedUpdateLo(irq, 0, IOAPIC_INT_MASK);
}
/**
@ -149,7 +149,7 @@ void z_ioapic_irq_enable(unsigned int irq)
*/
void z_ioapic_irq_disable(unsigned int irq)
{
_IoApicRedUpdateLo(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK);
IoApicRedUpdateLo(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK);
}
@ -312,7 +312,7 @@ void z_ioapic_irq_set(unsigned int irq, unsigned int vector, u32_t flags)
*/
void z_ioapic_int_vec_set(unsigned int irq, unsigned int vector)
{
_IoApicRedUpdateLo(irq, vector, IOAPIC_VEC_MASK);
IoApicRedUpdateLo(irq, vector, IOAPIC_VEC_MASK);
}
/**
@ -428,7 +428,7 @@ static void ioApicRedSetHi(unsigned int irq, u32_t upper32)
* @param mask Mask of bits to be modified
* @return N/A
*/
static void _IoApicRedUpdateLo(unsigned int irq,
static void IoApicRedUpdateLo(unsigned int irq,
u32_t value,
u32_t mask)
{

16
drivers/interrupt_controller/loapic_intr.c
View file

@ -47,7 +47,7 @@
* local APIC have been extended and/or modified in the local xAPIC.
*
* This driver contains three routines for use. They are:
* _loapic_init() initializes the Local APIC for the interrupt mode chosen.
* z_loapic_init() initializes the Local APIC for the interrupt mode chosen.
* _loapic_enable()/disable() enables / disables the Local APIC.
*
* Local APIC is used in the Virtual Wire Mode: delivery mode ExtINT.
@ -216,7 +216,7 @@ static ALWAYS_INLINE void LOAPIC_WRITE(mem_addr_t addr, u32_t data)
*
*/
static int _loapic_init(struct device *unused)
static int loapic_init(struct device *unused)
{
ARG_UNUSED(unused);
s32_t loApicMaxLvt; /* local APIC Max LVT */
@ -459,9 +459,9 @@ int loapic_resume(struct device *port)
ARG_UNUSED(port);
/* Assuming all loapic device registers lose their state, the call to
* _loapic_init(), should bring all the registers to a sane state.
* z_loapic_init(), should bring all the registers to a sane state.
*/
_loapic_init(NULL);
loapic_init(NULL);
for (loapic_irq = 0; loapic_irq < LOAPIC_IRQ_COUNT; loapic_irq++) {
@ -507,17 +507,17 @@ static int loapic_device_ctrl(struct device *port, u32_t ctrl_command,
return ret;
}
SYS_DEVICE_DEFINE("loapic", _loapic_init, loapic_device_ctrl, PRE_KERNEL_1,
SYS_DEVICE_DEFINE("loapic", loapic_init, loapic_device_ctrl, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#else
SYS_INIT(_loapic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
SYS_INIT(loapic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
#if CONFIG_LOAPIC_SPURIOUS_VECTOR
extern void _loapic_spurious_handler(void);
extern void z_loapic_spurious_handler(void);
NANO_CPU_INT_REGISTER(_loapic_spurious_handler, NANO_SOFT_IRQ,
NANO_CPU_INT_REGISTER(z_loapic_spurious_handler, NANO_SOFT_IRQ,
LOAPIC_SPURIOUS_VECTOR_ID >> 4,
LOAPIC_SPURIOUS_VECTOR_ID, 0);
#endif

4
drivers/interrupt_controller/loapic_spurious.S
View file

@ -12,8 +12,8 @@
#include <kernel_structs.h>
#include <arch/x86/asm.h>
GTEXT(_loapic_spurious_handler)
GTEXT(z_loapic_spurious_handler)
SECTION_FUNC(TEXT, _loapic_spurious_handler)
SECTION_FUNC(TEXT, z_loapic_spurious_handler)
iret

16
drivers/interrupt_controller/mvic.c
View file

@ -62,7 +62,7 @@ static inline u32_t compute_ioregsel(unsigned int irq)
*
* @returns N/A
*/
static void _mvic_rte_set(unsigned int irq, u32_t value)
static void mvic_rte_set(unsigned int irq, u32_t value)
{
unsigned int key; /* interrupt lock level */
u32_t regsel;
@ -92,7 +92,7 @@ static void _mvic_rte_set(unsigned int irq, u32_t value)
*
* @returns N/A
*/
static void _mvic_rte_update(unsigned int irq, u32_t value, u32_t mask)
static void mvic_rte_update(unsigned int irq, u32_t value, u32_t mask)
{
unsigned int key;
u32_t regsel, old_value, updated_value;
@ -123,14 +123,14 @@ static void _mvic_rte_update(unsigned int irq, u32_t value, u32_t mask)
*
* @returns: N/A
*/
static int _mvic_init(struct device *unused)
static int mvic_init(struct device *unused)
{
ARG_UNUSED(unused);
int i;
/* By default mask all interrupt lines */
for (i = 0; i < MVIC_NUM_RTES; i++) {
_mvic_rte_set(i, MVIC_IOWIN_MASK);
mvic_rte_set(i, MVIC_IOWIN_MASK);
}
/* reset the task priority and timer initial count registers */
@ -151,7 +151,7 @@ static int _mvic_init(struct device *unused)
return 0;
}
SYS_INIT(_mvic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
SYS_INIT(mvic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
void z_arch_irq_enable(unsigned int irq)
@ -160,7 +160,7 @@ void z_arch_irq_enable(unsigned int irq)
sys_write32(sys_read32(MVIC_LVTTIMER) & ~MVIC_LVTTIMER_MASK,
MVIC_LVTTIMER);
} else {
_mvic_rte_update(irq, 0, MVIC_IOWIN_MASK);
mvic_rte_update(irq, 0, MVIC_IOWIN_MASK);
}
}
@ -171,7 +171,7 @@ void z_arch_irq_disable(unsigned int irq)
sys_write32(sys_read32(MVIC_LVTTIMER) | MVIC_LVTTIMER_MASK,
MVIC_LVTTIMER);
} else {
_mvic_rte_update(irq, MVIC_IOWIN_MASK, MVIC_IOWIN_MASK);
mvic_rte_update(irq, MVIC_IOWIN_MASK, MVIC_IOWIN_MASK);
}
}
@ -186,7 +186,7 @@ void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
* interrupts need their triggering set
*/
if (irq != CONFIG_MVIC_TIMER_IRQ) {
_mvic_rte_set(irq, MVIC_IOWIN_MASK | flags);
mvic_rte_set(irq, MVIC_IOWIN_MASK | flags);
} else {
__ASSERT(flags == 0U,
"Timer interrupt cannot have triggering flags set");

6
drivers/modem/wncm14a2a.c
View file

@ -211,7 +211,7 @@ static void wncm14a2a_read_rx(struct net_buf **buf);
/*** Verbose Debugging Functions ***/
#if defined(ENABLE_VERBOSE_MODEM_RECV_HEXDUMP)
static inline void _hexdump(const u8_t *packet, size_t length)
static inline void hexdump(const u8_t *packet, size_t length)
{
char output[sizeof("xxxxyyyy xxxxyyyy")];
int n = 0, k = 0;
@ -261,7 +261,7 @@ static inline void _hexdump(const u8_t *packet, size_t length)
}
}
#else
#define _hexdump(...)
#define hexdump(...)
#endif
static struct wncm14a2a_socket *socket_get(void)
@ -1058,7 +1058,7 @@ static void wncm14a2a_read_rx(struct net_buf **buf)
break;
}
_hexdump(uart_buffer, bytes_read);
hexdump(uart_buffer, bytes_read);
/* make sure we have storage */
if (!*buf) {

4
drivers/pinmux/stm32/pinmux_stm32.c
View file

@ -122,7 +122,7 @@ static int stm32_pin_configure(int pin, int func, int altf)
*
* @return 0 on success, error otherwise
*/
int _pinmux_stm32_set(u32_t pin, u32_t func,
int z_pinmux_stm32_set(u32_t pin, u32_t func,
struct device *clk)
{
/* make sure to enable port clock first */
@ -148,7 +148,7 @@ void stm32_setup_pins(const struct pin_config *pinconf,
clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
for (i = 0; i < pins; i++) {
_pinmux_stm32_set(pinconf[i].pin_num,
z_pinmux_stm32_set(pinconf[i].pin_num,
pinconf[i].mode,
clk);
}

2
drivers/pinmux/stm32/pinmux_stm32.h
View file

@ -77,7 +77,7 @@ clock_control_subsys_t stm32_get_port_clock(int port);
* @param clk clock control device, for enabling/disabling clock gate
* for the port
*/
int _pinmux_stm32_set(u32_t pin, u32_t func,
int z_pinmux_stm32_set(u32_t pin, u32_t func,
struct device *clk);
/**

4
drivers/pwm/pwm_nrfx.c
View file

@ -360,7 +360,7 @@ static int pwm_nrfx_pm_control(struct device *dev,
.countertop = NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE, \
.prescaler = NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK \
}; \
static const struct pwm_nrfx_config pwm_nrfx_##idx##_config = { \
static const struct pwm_nrfx_config pwm_nrfx_##idx##z_config = { \
.pwm = NRFX_PWM_INSTANCE(idx), \
.initial_config = { \
.output_pins = { \
@ -383,7 +383,7 @@ static int pwm_nrfx_pm_control(struct device *dev,
DT_NORDIC_NRF_PWM_PWM_##idx##_LABEL, \
pwm_nrfx_init, pwm_##idx##_nrfx_pm_control, \
&pwm_nrfx_##idx##_data, \
&pwm_nrfx_##idx##_config, \
&pwm_nrfx_##idx##z_config, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&pwm_nrfx_drv_api_funcs)

4
drivers/pwm/pwm_pca9685.c
View file

@ -43,7 +43,7 @@
* @param dev Device struct.
* @return 1 if I2C master is identified, 0 if not.
*/
static inline int _has_i2c_master(struct device *dev)
static inline int has_i2c_master(struct device *dev)
{
struct pwm_pca9685_drv_data * const drv_data =
(struct pwm_pca9685_drv_data * const)dev->driver_data;
@ -71,7 +71,7 @@ static int pwm_pca9685_pin_set_cycles(struct device *dev, u32_t pwm,
u8_t buf[] = { 0, 0, 0, 0, 0};
ARG_UNUSED(period_count);
if (!_has_i2c_master(dev)) {
if (!has_i2c_master(dev)) {
return -EINVAL;
}

2
drivers/pwm/pwm_sifive.c
View file

@ -14,7 +14,7 @@ LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
/* Macros */
#define PWM_REG(_config, _offset) ((mem_addr_t) ((_config)->base + _offset))
#define PWM_REG(z_config, _offset) ((mem_addr_t) ((z_config)->base + _offset))
/* Register Offsets */
#define REG_PWMCFG 0x00

4
drivers/serial/uart_nrfx_uarte.c
View file

@ -1231,7 +1231,7 @@ static int uarte_nrfx_pm_control(struct device *dev, u32_t ctrl_command,
(.int_driven = &uarte##idx##_int_driven,), \
()) \
}; \
static const struct uarte_nrfx_config uarte_##idx##_config = { \
static const struct uarte_nrfx_config uarte_##idx##z_config = { \
.uarte_regs = (NRF_UARTE_Type *) \
DT_NORDIC_NRF_UARTE_UART_##idx##_BASE_ADDRESS, \
.rts_cts_pins_set = IS_ENABLED(UARTE_##idx##_CONFIG_RTS_CTS), \
@ -1273,7 +1273,7 @@ static int uarte_nrfx_pm_control(struct device *dev, u32_t ctrl_command,
uarte_##idx##_init, \
uarte_nrfx_pm_control, \
&uarte_##idx##_data, \
&uarte_##idx##_config, \
&uarte_##idx##z_config, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&uart_nrfx_uarte_driver_api)

4
drivers/spi/spi_context.h
View file

@ -51,10 +51,10 @@ struct spi_context {
};
#define SPI_CONTEXT_INIT_LOCK(_data, _ctx_name) \
._ctx_name.lock = _K_SEM_INITIALIZER(_data._ctx_name.lock, 0, 1)
._ctx_name.lock = Z_SEM_INITIALIZER(_data._ctx_name.lock, 0, 1)
#define SPI_CONTEXT_INIT_SYNC(_data, _ctx_name) \
._ctx_name.sync = _K_SEM_INITIALIZER(_data._ctx_name.sync, 0, 1)
._ctx_name.sync = Z_SEM_INITIALIZER(_data._ctx_name.sync, 0, 1)
static inline bool spi_context_configured(struct spi_context *ctx,
const struct spi_config *config)

36
drivers/spi/spi_dw.c
View file

@ -508,8 +508,8 @@ int spi_dw_init(struct device *dev)
const struct spi_dw_config *info = dev->config->config_info;
struct spi_dw_data *spi = dev->driver_data;
_clock_config(dev);
_clock_on(dev);
clock_config(dev);
clock_on(dev);
info->config_func();
@ -554,7 +554,7 @@ void spi_config_0_irq(void)
IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_0_IRQ);
_spi_int_unmask(SPI_DW_PORT_0_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_0_INT_MASK);
#else
IRQ_CONNECT(DT_SPI_0_IRQ_RX_AVAIL, DT_SPI_0_IRQ_RX_AVAIL_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS);
@ -567,9 +567,9 @@ void spi_config_0_irq(void)
irq_enable(DT_SPI_0_IRQ_TX_REQ);
irq_enable(DT_SPI_0_IRQ_ERR_INT);
_spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_0_ERROR_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_0_ERROR_INT_MASK);
#endif
}
#endif /* CONFIG_SPI_0 */
@ -602,7 +602,7 @@ void spi_config_1_irq(void)
IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_1_IRQ);
_spi_int_unmask(SPI_DW_PORT_1_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_1_INT_MASK);
#else
IRQ_CONNECT(DT_SPI_1_IRQ_RX_AVAIL, DT_SPI_1_IRQ_RX_AVAIL_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS);
@ -615,9 +615,9 @@ void spi_config_1_irq(void)
irq_enable(DT_SPI_1_IRQ_TX_REQ);
irq_enable(DT_SPI_1_IRQ_ERR_INT);
_spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_1_ERROR_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_1_ERROR_INT_MASK);
#endif
}
#endif /* CONFIG_SPI_1 */
@ -650,7 +650,7 @@ void spi_config_2_irq(void)
IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_2_IRQ);
_spi_int_unmask(SPI_DW_PORT_2_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_2_INT_MASK);
#else
IRQ_CONNECT(DT_SPI_2_IRQ_RX_AVAIL, DT_SPI_2_IRQ_RX_AVAIL_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS);
@ -663,9 +663,9 @@ void spi_config_2_irq(void)
irq_enable(DT_SPI_2_IRQ_TX_REQ);
irq_enable(DT_SPI_2_IRQ_ERR_INT);
_spi_int_unmask(SPI_DW_PORT_2_RX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_2_TX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_2_ERROR_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_2_RX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_2_TX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_2_ERROR_INT_MASK);
#endif
}
#endif /* CONFIG_SPI_2 */
@ -698,7 +698,7 @@ void spi_config_3_irq(void)
IRQ_CONNECT(DT_SPI_3_IRQ, DT_SPI_3_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_3_IRQ);
_spi_int_unmask(SPI_DW_PORT_3_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_3_INT_MASK);
#else
IRQ_CONNECT(DT_SPI_3_IRQ_RX_AVAIL, DT_SPI_3_IRQ_RX_AVAIL_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS);
@ -711,9 +711,9 @@ void spi_config_3_irq(void)
irq_enable(DT_SPI_3_IRQ_TX_REQ);
irq_enable(DT_SPI_3_IRQ_ERR_INT);
_spi_int_unmask(SPI_DW_PORT_3_RX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_3_TX_INT_MASK);
_spi_int_unmask(SPI_DW_PORT_3_ERROR_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_3_RX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_3_TX_INT_MASK);
z_spi_int_unmask(SPI_DW_PORT_3_ERROR_INT_MASK);
#endif
}
#endif /* CONFIG_SPI_3 */

54
drivers/spi/spi_dw.h
View file

@ -53,46 +53,46 @@ struct spi_dw_data {
#ifdef CONFIG_SPI_DW_ARC_AUX_REGS
#define _REG_READ(__sz) sys_in##__sz
#define _REG_WRITE(__sz) sys_out##__sz
#define _REG_SET_BIT sys_io_set_bit
#define _REG_CLEAR_BIT sys_io_clear_bit
#define _REG_TEST_BIT sys_io_test_bit
#define Z_REG_READ(__sz) sys_in##__sz
#define Z_REG_WRITE(__sz) sys_out##__sz
#define Z_REG_SET_BIT sys_io_set_bit
#define Z_REG_CLEAR_BIT sys_io_clear_bit
#define Z_REG_TEST_BIT sys_io_test_bit
#else
#define _REG_READ(__sz) sys_read##__sz
#define _REG_WRITE(__sz) sys_write##__sz
#define _REG_SET_BIT sys_set_bit
#define _REG_CLEAR_BIT sys_clear_bit
#define _REG_TEST_BIT sys_test_bit
#define Z_REG_READ(__sz) sys_read##__sz
#define Z_REG_WRITE(__sz) sys_write##__sz
#define Z_REG_SET_BIT sys_set_bit
#define Z_REG_CLEAR_BIT sys_clear_bit
#define Z_REG_TEST_BIT sys_test_bit
#endif /* CONFIG_SPI_DW_ARC_AUX_REGS */
#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
static inline u32_t read_##__reg(u32_t addr) \
{ \
return _REG_READ(__sz)(addr + __off); \
return Z_REG_READ(__sz)(addr + __off); \
}
#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
static inline void write_##__reg(u32_t data, u32_t addr) \
{ \
_REG_WRITE(__sz)(data, addr + __off); \
Z_REG_WRITE(__sz)(data, addr + __off); \
}
#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline void set_bit_##__reg_bit(u32_t addr) \
{ \
_REG_SET_BIT(addr + __reg_off, __bit); \
Z_REG_SET_BIT(addr + __reg_off, __bit); \
}
#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline void clear_bit_##__reg_bit(u32_t addr) \
{ \
_REG_CLEAR_BIT(addr + __reg_off, __bit); \
Z_REG_CLEAR_BIT(addr + __reg_off, __bit); \
}
#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline int test_bit_##__reg_bit(u32_t addr) \
{ \
return _REG_TEST_BIT(addr + __reg_off, __bit); \
return Z_REG_TEST_BIT(addr + __reg_off, __bit); \
}
/* Common registers settings, bits etc... */
@ -206,8 +206,8 @@ struct spi_dw_data {
#else
#include "spi_dw_regs.h"
#define _extra_clock_on(...)
#define _extra_clock_off(...)
#define z_extra_clock_on(...)
#define z_extra_clock_off(...)
#endif
@ -221,10 +221,10 @@ struct spi_dw_data {
#define _INT_UNMASK INT_UNMASK_IA
#endif
#define _spi_int_unmask(__mask) \
#define z_spi_int_unmask(__mask) \
sys_write32(sys_read32(__mask) & _INT_UNMASK, __mask)
#else
#define _spi_int_unmask(...)
#define z_spi_int_unmask(...)
#endif /* CONFIG_SOC_QUARK_SE_C1000 || CONFIG_SOC_QUARK_SE_C1000_SS */
/* Based on those macros above, here are common helpers for some registers */
@ -244,7 +244,7 @@ DEFINE_TEST_BIT_OP(sr_busy, DW_SPI_REG_SR, DW_SPI_SR_BUSY_BIT)
#include <string.h>
static inline int _clock_config(struct device *dev)
static inline int clock_config(struct device *dev)
{
const struct spi_dw_config *info = dev->config->config_info;
struct spi_dw_data *spi = dev->driver_data;
@ -262,7 +262,7 @@ static inline int _clock_config(struct device *dev)
return 0;
}
static inline void _clock_on(struct device *dev)
static inline void clock_on(struct device *dev)
{
struct spi_dw_data *spi = dev->driver_data;
@ -272,10 +272,10 @@ static inline void _clock_on(struct device *dev)
clock_control_on(spi->clock, info->clock_data);
}
_extra_clock_on(dev);
extra_clock_on(dev);
}
static inline void _clock_off(struct device *dev)
static inline void clock_off(struct device *dev)
{
struct spi_dw_data *spi = dev->driver_data;
@ -285,12 +285,12 @@ static inline void _clock_off(struct device *dev)
clock_control_off(spi->clock, info->clock_data);
}
_extra_clock_off(dev);
extra_clock_off(dev);
}
#else
#define _clock_config(...)
#define _clock_on(...)
#define _clock_off(...)
#define clock_config(...)
#define clock_on(...)
#define clock_off(...)
#endif /* CONFIG_CLOCK_CONTROL */
#ifdef __cplusplus

4
drivers/spi/spi_dw_quark_se_ss_regs.h
View file

@ -132,14 +132,14 @@ static inline u32_t read_dr(u32_t addr)
DEFINE_SET_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
DEFINE_CLEAR_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
static inline void _extra_clock_on(struct device *dev)
static inline void extra_clock_on(struct device *dev)
{
const struct spi_dw_config *info = dev->config->config_info;
set_bit_clk_ena(info->regs);
}
static inline void _extra_clock_off(struct device *dev)
static inline void extra_clock_off(struct device *dev)
{
const struct spi_dw_config *info = dev->config->config_info;

4
drivers/spi/spi_nrfx_spi.c
View file

@ -294,13 +294,13 @@ static int init_spi(struct device *dev, const nrfx_spi_config_t *config)
SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx), \
.busy = false, \
}; \
static const struct spi_nrfx_config spi_##idx##_config = { \
static const struct spi_nrfx_config spi_##idx##z_config = { \
.spi = NRFX_SPI_INSTANCE(idx), \
}; \
DEVICE_AND_API_INIT(spi_##idx, DT_NORDIC_NRF_SPI_SPI_##idx##_LABEL, \
spi_##idx##_init, \
&spi_##idx##_data, \
&spi_##idx##_config, \
&spi_##idx##z_config, \
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_nrfx_driver_api)

4
drivers/spi/spi_nrfx_spim.c
View file

@ -331,7 +331,7 @@ static int init_spim(struct device *dev, const nrfx_spim_config_t *config)
SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx), \
.busy = false, \
}; \
static const struct spi_nrfx_config spi_##idx##_config = { \
static const struct spi_nrfx_config spi_##idx##z_config = { \
.spim = NRFX_SPIM_INSTANCE(idx), \
.max_chunk_len = (1 << SPIM##idx##_EASYDMA_MAXCNT_SIZE) - 1, \
}; \
@ -339,7 +339,7 @@ static int init_spim(struct device *dev, const nrfx_spim_config_t *config)
DT_NORDIC_NRF_SPI_SPI_##idx##_LABEL, \
spi_##idx##_init, \
&spi_##idx##_data, \
&spi_##idx##_config, \
&spi_##idx##z_config, \
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_nrfx_driver_api)

4
drivers/spi/spi_nrfx_spis.c
View file

@ -271,7 +271,7 @@ static int init_spis(struct device *dev, const nrfx_spis_config_t *config)
SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx), \
}; \
static const struct spi_nrfx_config spi_##idx##_config = { \
static const struct spi_nrfx_config spi_##idx##z_config = { \
.spis = NRFX_SPIS_INSTANCE(idx), \
.max_buf_len = (1 << SPIS##idx##_EASYDMA_MAXCNT_SIZE) - 1, \
}; \
@ -279,7 +279,7 @@ static int init_spis(struct device *dev, const nrfx_spis_config_t *config)
DT_NORDIC_NRF_SPIS_SPI_##idx##_LABEL, \
spi_##idx##_init, \
&spi_##idx##_data, \
&spi_##idx##_config, \
&spi_##idx##z_config, \
POST_KERNEL, \
CONFIG_SPI_INIT_PRIORITY, \
&spi_nrfx_driver_api)

4
drivers/timer/arcv2_timer0.c
View file

@ -129,7 +129,7 @@ static u32_t elapsed(void)
*
* @return N/A
*/
static void _timer_int_handler(void *unused)
static void timer_int_handler(void *unused)
{
ARG_UNUSED(unused);
u32_t dticks;
@ -164,7 +164,7 @@ int z_clock_driver_init(struct device *device)
last_load = CYC_PER_TICK;
IRQ_CONNECT(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY,
_timer_int_handler, NULL, 0);
timer_int_handler, NULL, 0);
timer0_limit_register_set(last_load - 1);
#ifdef CONFIG_BOOT_TIME_MEASUREMENT

14
drivers/timer/legacy_api.h
View file

@ -10,15 +10,15 @@
*/
#ifdef CONFIG_TICKLESS_IDLE
void _timer_idle_enter(s32_t ticks);
void z_timer_idle_enter(s32_t ticks);
void z_clock_idle_exit(void);
#endif
#ifdef CONFIG_TICKLESS_KERNEL
void _set_time(u32_t time);
extern u32_t _get_program_time(void);
extern u32_t _get_remaining_program_time(void);
extern u32_t _get_elapsed_program_time(void);
void z_set_time(u32_t time);
extern u32_t z_get_program_time(void);
extern u32_t z_get_remaining_program_time(void);
extern u32_t z_get_elapsed_program_time(void);
#endif
extern u64_t z_clock_uptime(void);
@ -27,9 +27,9 @@ void z_clock_set_timeout(s32_t ticks, bool idle)
{
#ifdef CONFIG_TICKLESS_KERNEL
if (idle) {
_timer_idle_enter(ticks);
z_timer_idle_enter(ticks);
} else {
_set_time(ticks == K_FOREVER ? 0 : ticks);
z_set_time(ticks == K_FOREVER ? 0 : ticks);
}
#endif
}

32
drivers/timer/loapic_timer.c
View file

@ -23,7 +23,7 @@
*
* If the TICKLESS_IDLE kernel configuration option is enabled, the timer may
* be programmed to wake the system in N >= TICKLESS_IDLE_THRESH ticks. The
* kernel invokes _timer_idle_enter() to program the down counter in one-shot
* kernel invokes z_timer_idle_enter() to program the down counter in one-shot
* mode to trigger an interrupt in N ticks. When the timer expires or when
* another interrupt is detected, the kernel's interrupt stub invokes
* z_clock_idle_exit() to leave the tickless idle state.
@ -45,7 +45,7 @@
* straddled, the following will occur:
* a. Enter tickless idle in one-shot mode
* b. Immediately leave tickless idle
* c. Process the tick event in the _timer_int_handler() and revert
* c. Process the tick event in the timer_int_handler() and revert
* to periodic mode.
* d. Re-run the scheduler and possibly re-enter tickless idle
*
@ -55,9 +55,9 @@
* 5. Tickless idle may be prematurely aborted due to a non-timer interrupt.
* Its handler may make a thread ready to run, so any elapsed ticks
* must be accounted for and the timer must also expire at the end of the
* next logical tick so _timer_int_handler() can put it back in periodic mode.
* next logical tick so timer_int_handler() can put it back in periodic mode.
* This can only be distinguished from the previous factor by the execution of
* _timer_int_handler().
* timer_int_handler().
*
* 6. Tickless idle may end naturally. The down counter should be zero in
* this case. However, some targets do not implement the local APIC timer
@ -277,7 +277,7 @@ static inline void program_max_cycles(void)
}
#endif
void _timer_int_handler(void *unused /* parameter is not used */
void timer_int_handler(void *unused /* parameter is not used */
)
{
#ifdef CONFIG_EXECUTION_BENCHMARKING
@ -380,12 +380,12 @@ void _timer_int_handler(void *unused /* parameter is not used */
}
#ifdef CONFIG_TICKLESS_KERNEL
u32_t _get_program_time(void)
u32_t z_get_program_time(void)
{
return programmed_full_ticks;
}
u32_t _get_remaining_program_time(void)
u32_t z_get_remaining_program_time(void)
{
if (programmed_full_ticks == 0U) {
return 0;
@ -394,7 +394,7 @@ u32_t _get_remaining_program_time(void)
return current_count_register_get() / cycles_per_tick;
}
u32_t _get_elapsed_program_time(void)
u32_t z_get_elapsed_program_time(void)
{
if (programmed_full_ticks == 0U) {
return 0;
@ -404,7 +404,7 @@ u32_t _get_elapsed_program_time(void)
(current_count_register_get() / cycles_per_tick);
}
void _set_time(u32_t time)
void z_set_time(u32_t time)
{
if (!time) {
programmed_full_ticks = 0U;
@ -479,14 +479,14 @@ static void tickless_idle_init(void)
*
* @return N/A
*/
void _timer_idle_enter(s32_t ticks /* system ticks */
void z_timer_idle_enter(s32_t ticks /* system ticks */
)
{
#ifdef CONFIG_TICKLESS_KERNEL
if (ticks != K_FOREVER) {
/* Need to reprogram only if current program is smaller */
if (ticks > programmed_full_ticks) {
_set_time(ticks);
z_set_time(ticks);
}
} else {
programmed_full_ticks = 0U;
@ -576,9 +576,9 @@ void z_clock_idle_exit(void)
if ((remaining_cycles == 0U) ||
(remaining_cycles >= programmed_cycles)) {
/*
* The timer has expired. The handler _timer_int_handler() is
* The timer has expired. The handler timer_int_handler() is
* guaranteed to execute. Track the number of elapsed ticks. The
* handler _timer_int_handler() will account for the final tick.
* handler timer_int_handler() will account for the final tick.
*/
_sys_idle_elapsed_ticks = programmed_full_ticks;
@ -612,7 +612,7 @@ void z_clock_idle_exit(void)
* NOTE #2: In the case of a straddled tick, it is assumed that when the
* timer is reprogrammed, it will be reprogrammed with a cycle count
* sufficiently close to one tick that the timer will not expire before
* _timer_int_handler() is executed.
* timer_int_handler() is executed.
*/
remaining_full_ticks = remaining_cycles / cycles_per_tick;
@ -669,7 +669,7 @@ int z_clock_driver_init(struct device *device)
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
loapic_timer_device_power_state = DEVICE_PM_ACTIVE_STATE;
#endif
IRQ_CONNECT(TIMER_IRQ, TIMER_IRQ_PRIORITY, _timer_int_handler, 0, 0);
IRQ_CONNECT(TIMER_IRQ, TIMER_IRQ_PRIORITY, timer_int_handler, 0, 0);
/* Everything has been configured. It is now safe to enable the
* interrupt
@ -782,7 +782,7 @@ u32_t z_timer_cycle_get_32(void)
/* TSC runs same as the bus speed, nothing to do but return the TSC
* value
*/
return _do_read_cpu_timestamp32();
return z_do_read_cpu_timestamp32();
#endif
}

2
drivers/timer/native_posix_timer.c
View file

@ -44,7 +44,7 @@ u32_t z_timer_cycle_get_32(void)
* if sys_ticks is K_FOREVER (or another negative number),
* we will effectively silence the tick interrupts forever
*/
void _timer_idle_enter(s32_t sys_ticks)
void z_timer_idle_enter(s32_t sys_ticks)
{
if (silent_ticks > 0) { /* LCOV_EXCL_BR_LINE */
/* LCOV_EXCL_START */

2
drivers/timer/xtensa_sys_timer.c
View file

@ -62,7 +62,7 @@ static void ccompare_isr(void *arg)
* pervasive.
*/
#ifndef CONFIG_XTENSA_ASM2
void _timer_int_handler(void *arg)
void timer_int_handler(void *arg)
{
return ccompare_isr(arg);
}

4
drivers/usb/device/usb_dc_dw.c
View file

@ -64,7 +64,7 @@ struct usb_dw_ctrl_prv {
static struct usb_dw_ctrl_prv usb_dw_ctrl;
static inline void _usb_dw_int_unmask(void)
static inline void usb_dw_int_unmask(void)
{
#if defined(CONFIG_SOC_QUARK_SE_C1000)
QM_INTERRUPT_ROUTER->usb_0_int_mask &= ~BIT(0);
@ -752,7 +752,7 @@ int usb_dc_attach(void)
usb_dw_isr_handler, 0, IOAPIC_EDGE | IOAPIC_HIGH);
irq_enable(USB_DW_IRQ);
_usb_dw_int_unmask();
usb_dw_int_unmask();
usb_dw_ctrl.attached = 1U;

4
drivers/watchdog/wdog_cmsdk_apb.c
View file

@ -145,7 +145,7 @@ static const struct wdt_driver_api wdog_cmsdk_apb_api = {
};
#ifdef CONFIG_RUNTIME_NMI
extern void _NmiHandlerSet(void (*pHandler)(void));
extern void z_NmiHandlerSet(void (*pHandler)(void));
static int wdog_cmsdk_apb_has_fired(void)
{
@ -186,7 +186,7 @@ static int wdog_cmsdk_apb_init(struct device *dev)
#ifdef CONFIG_RUNTIME_NMI
/* Configure the interrupts */
_NmiHandlerSet(wdog_cmsdk_apb_isr);
z_NmiHandlerSet(wdog_cmsdk_apb_isr);
#endif
#ifdef CONFIG_WDOG_CMSDK_APB_START_AT_BOOT

16
drivers/wifi/simplelink/simplelink.c
View file

@ -92,7 +92,7 @@ static void simplelink_scan_work_handler(struct k_work *work)
/* Iterate over the table, and call the scan_result callback. */
while (index < simplelink_data.num_results_or_err) {
_simplelink_get_scan_result(index, &scan_result);
z_simplelink_get_scan_result(index, &scan_result);
simplelink_data.cb(simplelink_data.iface, 0,
&scan_result);
/* Yield, to ensure notifications get delivered: */
@ -112,7 +112,7 @@ static void simplelink_scan_work_handler(struct k_work *work)
s32_t delay;
/* Try again: */
simplelink_data.num_results_or_err = _simplelink_start_scan();
simplelink_data.num_results_or_err = z_simplelink_start_scan();
simplelink_data.scan_retries++;
delay = (simplelink_data.num_results_or_err > 0 ? 0 :
SCAN_RETRY_DELAY);
@ -139,7 +139,7 @@ static int simplelink_mgmt_scan(struct device *dev, scan_result_cb_t cb)
k_delayed_work_cancel(&simplelink_data.work);
/* "Request" the scan: */
err = _simplelink_start_scan();
err = z_simplelink_start_scan();
/* Now, launch a delayed work handler to do retries and reporting.
* Indicate (to the work handler) either a positive number of results
@ -167,7 +167,7 @@ static int simplelink_mgmt_connect(struct device *dev,
{
int ret;
ret = _simplelink_connect(params);
ret = z_simplelink_connect(params);
return ret ? -EIO : ret;
}
@ -176,7 +176,7 @@ static int simplelink_mgmt_disconnect(struct device *dev)
{
int ret;
ret = _simplelink_disconnect();
ret = z_simplelink_disconnect();
return ret ? -EIO : ret;
}
@ -215,9 +215,9 @@ static void simplelink_iface_init(struct net_if *iface)
iface->if_dev->offload = &simplelink_offload;
/* Initialize and configure NWP to defaults: */
ret = _simplelink_init(simplelink_wifi_cb);
ret = z_simplelink_init(simplelink_wifi_cb);
if (ret) {
LOG_ERR("_simplelink_init failed!");
LOG_ERR("z_simplelink_init failed!");
return;
}
@ -229,7 +229,7 @@ static void simplelink_iface_init(struct net_if *iface)
}
/* Grab our MAC address: */
_simplelink_get_mac(simplelink_data.mac);
z_simplelink_get_mac(simplelink_data.mac);
LOG_DBG("MAC Address %02X:%02X:%02X:%02X:%02X:%02X",
simplelink_data.mac[0], simplelink_data.mac[1],

12
drivers/wifi/simplelink/simplelink_support.c
View file

@ -488,7 +488,7 @@ void SimpleLinkNetAppRequestMemFreeEventHandler(u8_t *buffer)
* - Whether network hidden or visible
* - Other types of security
*/
void _simplelink_get_scan_result(int index,
void z_simplelink_get_scan_result(int index,
struct wifi_scan_result *scan_result)
{
SlWlanNetworkEntry_t *net_entry;
@ -515,7 +515,7 @@ void _simplelink_get_scan_result(int index,
scan_result->rssi = net_entry->Rssi;
}
int _simplelink_start_scan(void)
int z_simplelink_start_scan(void)
{
s32_t ret;
@ -533,7 +533,7 @@ int _simplelink_start_scan(void)
return ret;
}
void _simplelink_get_mac(unsigned char *mac)
void z_simplelink_get_mac(unsigned char *mac)
{
u16_t mac_len = SL_MAC_ADDR_LEN;
u16_t config_opt = 0U;
@ -542,7 +542,7 @@ void _simplelink_get_mac(unsigned char *mac)
&mac_len, (u8_t *)mac);
}
int _simplelink_connect(struct wifi_connect_req_params *params)
int z_simplelink_connect(struct wifi_connect_req_params *params)
{
SlWlanSecParams_t secParams = { 0 };
long lretval;
@ -565,7 +565,7 @@ int _simplelink_connect(struct wifi_connect_req_params *params)
return lretval;
}
int _simplelink_disconnect(void)
int z_simplelink_disconnect(void)
{
long lretval;
@ -575,7 +575,7 @@ int _simplelink_disconnect(void)
return lretval;
}
int _simplelink_init(simplelink_wifi_cb_t wifi_cb)
int z_simplelink_init(simplelink_wifi_cb_t wifi_cb)
{
int retval;

12
drivers/wifi/simplelink/simplelink_support.h
View file

@ -35,13 +35,13 @@ struct sl_connect_state {
typedef void (*simplelink_wifi_cb_t)(u32_t mgmt_event,
struct sl_connect_state *conn);
extern int _simplelink_start_scan(void);
extern void _simplelink_get_scan_result(int index,
extern int z_simplelink_start_scan(void);
extern void z_simplelink_get_scan_result(int index,
struct wifi_scan_result *scan_result);
extern void _simplelink_get_mac(unsigned char *mac);
extern int _simplelink_init(simplelink_wifi_cb_t wifi_cb);
extern int _simplelink_connect(struct wifi_connect_req_params *params);
extern int _simplelink_disconnect(void);
extern void z_simplelink_get_mac(unsigned char *mac);
extern int z_simplelink_init(simplelink_wifi_cb_t wifi_cb);
extern int z_simplelink_connect(struct wifi_connect_req_params *params);
extern int z_simplelink_disconnect(void);
#ifdef __cplusplus
}

2
ext/hal/cypress/PDL/3.1.0/drivers/include/cy_sysclk.h
View file

@ -29,7 +29,7 @@
* clock system.
*
* The PDL defines clock system capabilities in:\n
* devices\<family\>/<series\>/include\<series\>_config.h. (E.g.
* devices\<family\>/<series\>/include\<series\>z_config.h. (E.g.
* devices/psoc6/psoc63/include/psoc63_config.h).
* User-configurable clock speeds are defined in the file system_<series>.h.
*

2
ext/hal/libmetal/libmetal/lib/system/zephyr/mutex.h
View file

@ -29,7 +29,7 @@ typedef struct k_sem metal_mutex_t;
* METAL_MUTEX_INIT - used for initializing an mutex elmenet in a static struct
* or global
*/
#define METAL_MUTEX_INIT(m) _K_SEM_INITIALIZER(m, 1, 1)
#define METAL_MUTEX_INIT(m) Z_SEM_INITIALIZER(m, 1, 1)
/*
* METAL_MUTEX_DEFINE - used for defining and initializing a global or
* static singleton mutex

2
ext/hal/nxp/mcux/drivers/imx/fsl_gpio.h
View file

@ -45,7 +45,7 @@ typedef enum _gpio_interrupt_mode
} gpio_interrupt_mode_t;
/*! @brief GPIO Init structure definition. */
typedef struct _gpio_pin_config
typedef struct z_gpio_pin_config
{
gpio_pin_direction_t direction; /*!< Specifies the pin direction. */
uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */

2
ext/hal/nxp/mcux/drivers/kinetis/fsl_gpio.h
View file

@ -65,7 +65,7 @@ typedef enum _gpio_checker_attribute
* Note that in some use cases, the corresponding port property should be configured in advance
* with the PORT_SetPinConfig().
*/
typedef struct _gpio_pin_config
typedef struct z_gpio_pin_config
{
gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
/* Output configurations; ignore if configured as an input pin */

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