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boards: mimxrt1015_evk: Enable SPI on RT1015

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This commit enables the LPSPI1 peripheral on the RT1015 EVK. LPSPI pins
are not populated by default, but headers can be added to J19 on the EVK
to access these signals

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2021-10-08 16:43:05 -05:00 • committed by Christopher Friedt
commit 97b138e8c9
6 changed files with 55 additions and 0 deletions
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10
boards/arm/mimxrt1015_evk/doc/index.rst
View file

@ -69,6 +69,8 @@ features:
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
@ -104,6 +106,14 @@ The MIMXRT1015 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_14 | LPI2C1_CLK | I2C SCL |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | LPSPI1_SCK | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_11 | LPSPI1_PCS0 | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_12 | LPSPI1_SDO | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | LPSPI1_SDI | SPI |
+---------------+-----------------+---------------------------+
System Clock
============

4
boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts
View file

@ -94,6 +94,10 @@ arduino_serial: &lpuart4 {};
current-speed = <115200>;
};
&lpspi1 {
status = "okay";
};
zephyr_udc0: &usb1 {
status = "okay";
};

1
boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml
View file

@ -21,3 +21,4 @@ supported:
- gpio
- i2c
- usb_device
- spi

29
boards/arm/mimxrt1015_evk/pinmux.c
View file

@ -77,6 +77,35 @@ static int mimxrt1015_evk_init(const struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI
/* LPSPI1 CS, SDO, SDI, CLK exposed as pins 3, 4, 5, and 6 on J19 */
/* GPIO_AD_B0_10 is configured as LPSPI1_SCK */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK, 0U);
/* GPIO_AD_B0_11 is configured as LPSPI1_PCS0 */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0, 0U);
/* GPIO_AD_B0_12 is configured as LPSPI1_SDO */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO, 0U);
/* GPIO_AD_B0_13 is configured as LPSPI1_SDI */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
return 0;
}

4
dts/arm/nxp/nxp_rt1015.dtsi
View file

@ -29,3 +29,7 @@
&gpt2 {
gptfreq = <12500000>;
};
/* RT1015 only has two LPSPI blocks */
/delete-node/ &lpspi3;
/delete-node/ &lpspi4;

7
tests/drivers/spi/spi_loopback/boards/mimxrt1015_evk.conf Normal file
View file

@ -0,0 +1,7 @@
#
# Copyright (c) 2021, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_1"