arch/xtensa: Promote adsp RPO/cache utilities to an arch API
This is trick (mapping RAM twice so you can use alternate Region Protection Option addresses to control cacheability) is something any Xtensa hardware designer might productively choose to do. And as it works really well, we should encourage that by making this a generic architecture feature for Zephyr. Now everything works by setting two kconfig values at the soc level defining the cached and uncached regions. As long as these are correct, you can then use the new arch_xtensa_un/cached_ptr() APIs to convert between them and a ARCH_XTENSA_SET_RPO_TLB() macro that provides much smaller initialization code (in C!) than the HAL assembly macros. The conversion routines have been generalized to support conversion between any two regions. Note that full KERNEL_COHERENCE still requires support from the platform linker script, that can't be made generic given the way Zephyr does linkage. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Carles Cufí
parent
6aa3d0c72f
commit
97ada8bc04
9 changed files with 191 additions and 125 deletions
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@ -15,8 +15,9 @@ extern "C" {
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#define Z_DCACHE_MAX (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
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#if XCHAL_DCACHE_SIZE
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#define Z_IS_POW2(x) (((x) != 0) && (((x) & ((x)-1)) == 0))
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#if XCHAL_DCACHE_SIZE
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BUILD_ASSERT(Z_IS_POW2(XCHAL_DCACHE_LINESIZE));
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BUILD_ASSERT(Z_IS_POW2(Z_DCACHE_MAX));
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#endif
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@ -78,6 +79,139 @@ static ALWAYS_INLINE void z_xtensa_cache_flush_inv_all(void)
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z_xtensa_cache_flush_inv(NULL, Z_DCACHE_MAX);
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}
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#ifdef CONFIG_ARCH_HAS_COHERENCE
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static inline bool arch_mem_coherent(void *ptr)
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{
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size_t addr = (size_t) ptr;
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return (addr >> 29) == CONFIG_XTENSA_UNCACHED_REGION;
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}
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#endif
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static ALWAYS_INLINE uint32_t z_xtrpoflip(uint32_t addr, uint32_t rto, uint32_t rfrom)
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{
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/* The math here is all compile-time: when the two regions
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* differ by a power of two, we can convert between them by
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* setting or clearing just one bit. Otherwise it needs two
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* operations.
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*/
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uint32_t rxor = (rto ^ rfrom) << 29;
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rto <<= 29;
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if (Z_IS_POW2(rxor)) {
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if ((rxor & rto) == 0) {
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return addr & ~rxor;
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} else {
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return addr | rxor;
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}
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} else {
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return (addr & ~(7U << 29)) | rto;
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}
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}
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/**
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* @brief Return cached pointer to a RAM address
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*
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* The Xtensa coherence architecture maps addressable RAM twice, in
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* two different 512MB regions whose L1 cache settings can be
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* controlled independently. So for any given pointer, it is possible
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* to convert it to and from a cached version.
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*
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* This function takes a pointer to any addressible object (either in
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* cacheable memory or not) and returns a pointer that can be used to
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* refer to the same memory through the L1 data cache. Data read
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* through the resulting pointer will reflect locally cached values on
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* the current CPU if they exist, and writes will go first into the
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* cache and be written back later.
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*
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* @see arch_xtensa_uncached_ptr()
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*
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* @param ptr A pointer to a valid C object
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* @return A pointer to the same object via the L1 dcache
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*/
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static inline void *arch_xtensa_cached_ptr(void *ptr)
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{
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return (void *)z_xtrpoflip((uint32_t) ptr,
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CONFIG_XTENSA_CACHED_REGION,
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CONFIG_XTENSA_UNCACHED_REGION);
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}
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/**
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* @brief Return uncached pointer to a RAM address
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*
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* The Xtensa coherence architecture maps addressable RAM twice, in
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* two different 512MB regions whose L1 cache settings can be
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* controlled independently. So for any given pointer, it is possible
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* to convert it to and from a cached version.
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*
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* This function takes a pointer to any addressible object (either in
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* cacheable memory or not) and returns a pointer that can be used to
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* refer to the same memory while bypassing the L1 data cache. Data
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* in the L1 cache will not be inspected nor modified by the access.
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*
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* @see arch_xtensa_cached_ptr()
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*
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* @param ptr A pointer to a valid C object
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* @return A pointer to the same object bypassing the L1 dcache
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*/
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static inline void *arch_xtensa_uncached_ptr(void *ptr)
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{
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return (void *)z_xtrpoflip((uint32_t) ptr,
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CONFIG_XTENSA_UNCACHED_REGION,
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CONFIG_XTENSA_CACHED_REGION);
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}
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/* Utility to generate an unrolled and optimal[1] code sequence to set
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* the RPO TLB registers (contra the HAL cacheattr macros, which
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* generate larger code and can't be called from C), based on the
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* KERNEL_COHERENCE configuration in use. Selects RPO attribute "2"
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* for regions (including MMIO registers in region zero) which want to
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* bypass L1, "4" for the cached region which wants writeback, and
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* "15" (invalid) elsewhere.
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*
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* Note that on cores that have the "translation" option set, we need
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* to put an identity mapping in the high bits. Also per spec
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* changing the current code region (by definition cached) requires
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* that WITLB be followed by an ISYNC and that both instructions live
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* in the same cache line (two 3-byte instructions fit in an 8-byte
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* aligned region, so that's guaranteed not to cross a cache line
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* boundary).
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*
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* [1] With the sole exception of gcc's infuriating insistence on
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* emitting a precomputed literal for addr + addrincr instead of
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* computing it with a single ADD instruction from values it already
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* has in registers. Explicitly assigning the variables to registers
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* via an attribute works, but then emits needless MOV instructions
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* instead. I tell myself it's just 32 bytes of .text, but... Sigh.
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*/
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#define _REGION_ATTR(r) \
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((r) == 0 ? 2 : \
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((r) == CONFIG_XTENSA_CACHED_REGION ? 4 : \
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((r) == CONFIG_XTENSA_UNCACHED_REGION ? 2 : 15)))
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#define _SET_ONE_TLB(region) do { \
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uint32_t attr = _REGION_ATTR(region); \
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if (XCHAL_HAVE_XLT_CACHEATTR) { \
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attr |= addr; /* RPO with translation */ \
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} \
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if (region != CONFIG_XTENSA_CACHED_REGION) { \
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__asm__ volatile("wdtlb %0, %1; witlb %0, %1" \
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:: "r"(attr), "r"(addr)); \
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} else { \
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__asm__ volatile("wdtlb %0, %1" \
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:: "r"(attr), "r"(addr)); \
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__asm__ volatile("j 1f; .align 8; 1:"); \
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__asm__ volatile("witlb %0, %1; isync" \
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:: "r"(attr), "r"(addr)); \
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} \
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addr += addrincr; \
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} while (0)
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#define ARCH_XTENSA_SET_RPO_TLB() do { \
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register uint32_t addr = 0, addrincr = 0x20000000; \
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FOR_EACH(_SET_ONE_TLB, (;), 0, 1, 2, 3, 4, 5, 6, 7); \
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} while (0)
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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