soc: nxp: mcx: Add MCXW72

Add MCXW72 SOC, SOC Kconfigs, and
Platform Init code

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>

soc/nxp/mcx/mcxw/CMakeLists.txt

@@ -2,7 +2,9 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(soc.c mcxw71_platform_init.S)
+zephyr_sources(soc.c)
+zephyr_sources_ifdef(CONFIG_SOC_MCXW716C mcxw71_platform_init.S)
+zephyr_sources_ifdef(CONFIG_SOC_MCXW727C mcxw72_platform_init.S)
 
 zephyr_sources_ifdef(CONFIG_NXP_NBU
   ../../common/nxp_nbu.c

soc/nxp/mcx/mcxw/Kconfig

@@ -17,3 +17,11 @@ config SOC_SERIES_MCXW
 	select CLOCK_CONTROL
 
 	rsource "../../common/Kconfig.nbu"
+
+if SOC_MCXW727C
+
+config MCUX_CORE_SUFFIX
+	default "_cm33_core0" if SOC_MCXW727C_CPU0
+	default "_cm33_core1" if SOC_MCXW727C_CPU1
+
+endif # SOC_MCXW727C

soc/nxp/mcx/mcxw/Kconfig.defconfig

@@ -4,6 +4,7 @@
 if SOC_SERIES_MCXW
 
 config NUM_IRQS
+	default 77 if SOC_MCXW727C
 	default 75
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC

soc/nxp/mcx/mcxw/Kconfig.soc

@@ -12,11 +12,28 @@ config SOC_MCXW716C
 	bool
 	select SOC_SERIES_MCXW
 
+config SOC_MCXW727C
+	bool
+	select SOC_SERIES_MCXW
+
+config SOC_MCXW727C_CPU0
+	bool
+	select SOC_MCXW727C
+
+config SOC_MCXW727C_CPU1
+	bool
+	select SOC_MCXW727C
+
 config SOC
 	default "mcxw716c" if SOC_MCXW716C
+	default "mcxw727c" if SOC_MCXW727C
 
 config SOC_PART_NUMBER_MCXW716CMFTA
 	bool
 
+config SOC_PART_NUMBER_MCXW727CMFTA
+	bool
+
 config SOC_PART_NUMBER
 	default "MCXW716CMFTA" if SOC_PART_NUMBER_MCXW716CMFTA
+	default "MCXW727CMFTA" if SOC_PART_NUMBER_MCXW727CMFTA

soc/nxp/mcx/mcxw/mcxw72_platform_init.S

@@ -0,0 +1,58 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief MCXW72 Platform-Specific Initialization
+ *
+ * When compared to MCXW71, the Ram Banks with ECC
+ * are located in different addresses.
+ *
+ * MCXW72 SOC reset code that initializes RAM
+ * to prevent ECC causing faults, and calls SystemInit
+ */
+
+#include <zephyr/toolchain.h>
+#include <zephyr/linker/sections.h>
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(soc_reset_hook)
+SECTION_SUBSEC_FUNC(TEXT,_reset_section,soc_reset_hook)
+
+.soc_reset_hook:
+    ldr r0, =0x14000000
+    ldr r1, =.ram_init_ctcm01
+    bics r1, #0x10000000
+    cmp r0, r1
+    bcc .ram_init_done
+.ram_init_ctcm01: /* Initialize ctcm01 */
+    ldr r0, =0x14000000
+    ldr r1, =0x14008000
+    ldr r2, =0
+    ldr r3, =0
+    ldr r4, =0
+    ldr r5, =0
+.loop01:
+    stmia r0!, {r2 - r5}
+    cmp r0, r1
+    bcc.n .loop01
+.ram_init_stcm012: /* Initialize stcm012 */
+    ldr r0, =0x30000000
+    ldr r1, =0x30010000
+.loop012:
+    stmia r0!, {r2 - r5}
+    cmp r0, r1
+    bcc.n .loop012
+.ram_init_stcm8:
+    ldr r0, =0x30038000
+    ldr r1, =0x3003a000
+.loop8: /* Initialize stcm5 */
+    stmia r0!, {r2 - r5}
+    cmp r0, r1
+    bcc.n .loop8
+.ram_init_done:
+    b SystemInit

soc/nxp/mcx/mcxw/soc.c

@@ -39,6 +39,7 @@ static ALWAYS_INLINE void clock_init(void)
 	};
 	/* Enable OSC32K */
 	CCM32K_Set32kOscConfig(CCM32K, kCCM32K_Enable32kHzCrystalOsc, &ccm32k_osc_config);
+
 	/* Disable ROSC Monitor, because switching the source would generate an expected error */
 	CLOCK_SetRoscMonitorMode(kSCG_RoscMonitorDisable);
 

soc/nxp/mcx/soc.yml

@@ -20,6 +20,10 @@ family:
   - name: mcxw
     socs:
     - name: mcxw716c
+    - name: mcxw727c
+      cpuclusters:
+      - name: cpu0
+      - name: cpu1
 runners:
   run_once:
     '--erase':