everywhere: fix typos

Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
This commit is contained in:
Nazar Kazakov 2022-02-24 12:00:55 +00:00 committed by Anas Nashif
commit 9713f0d47c
331 changed files with 478 additions and 478 deletions

View file

@ -9,5 +9,5 @@ config NPCX_MIWU
depends on SOC_FAMILY_NPCX
help
This option enables the Multi-Input Wake-Up Unit (MIWU) driver
for NPCX family ofprocessors.
for NPCX family of processors.
This is required for GPIO, RTC, LPC/eSPI interrupt support.

View file

@ -43,7 +43,7 @@
#define GICR_PROPBASER 0x0070
#define GICR_PENDBASER 0x0078
/* Register bit definations */
/* Register bit definitions */
/* GICD_CTLR Interrupt group definitions */
#define GICD_CTLR_ENABLE_G0 0

View file

@ -76,7 +76,7 @@ struct xec_girq_src_data {
((struct xec_girq_src_data *const)(girq_dev)->data)
/*
* Enable/disable specified GIRQ's aggregated output. Aggrated output is the
* Enable/disable specified GIRQ's aggregated output. Aggregated output is the
* bit-wise or of all the GIRQ's result bits.
*/
void mchp_xec_ecia_girq_aggr_en(uint8_t girq_num, uint8_t enable)
@ -229,7 +229,7 @@ uint32_t mchp_xec_ecia_info_girq_result(int ecia_info)
/*
* Clear NVIC pending status given GIRQ source information encoded by macro
* MCHP_XEC_ECIA. For aggregated only sources the ecoding sets direct NVIC
* MCHP_XEC_ECIA. For aggregated only sources the encoding sets direct NVIC
* number equal to aggregated NVIC number.
*/
void mchp_xec_ecia_info_nvic_clr_pend(int ecia_info)

View file

@ -18,7 +18,7 @@
* MIWU2. Together, they support a total of over 140 internal and/or external
* wake-up input (WUI) sources.
*
* This driver uses device tree files to present the relationship bewteen
* This driver uses device tree files to present the relationship between
* MIWU and the other devices in different npcx series. For npcx7 series,
* it include:
* 1. npcxn-miwus-wui-map.dtsi: it presents relationship between wake-up inputs
@ -143,7 +143,7 @@ static void intc_miwu_isr_pri(int wui_table, int wui_group)
if (mask & BIT(wui_bit)) {
LOG_DBG("miwu_isr %d %d %d!\n", wui_table,
wui_group, wui_bit);
/* Dispatch registed gpio and generic isrs */
/* Dispatch registered gpio and generic isrs */
intc_miwu_dispatch_gpio_isr(wui_table,
wui_group, wui_bit);
intc_miwu_dispatch_generic_isr(wui_table,