michaelh/zephyr
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everywhere: fix typos

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Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
This commit is contained in:
Nazar Kazakov 2022-02-24 12:00:55 +00:00 • committed by Anas Nashif
commit 9713f0d47c
331 changed files with 478 additions and 478 deletions
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6
drivers/disk/sdmmc_sdhc.h
View file

@ -324,13 +324,13 @@ enum sd_max_current {
enum sd_voltage {
SD_VOL_NONE = 0U,
/*!< indicate current voltage setting is not setting bu suser*/
/*!< indicate current voltage setting is not set by user*/
SD_VOL_3_3_V = 1U,
/*!< card operation voltage around 3.3v */
SD_VOL_3_0_V = 2U,
/*!< card operation voltage around 3.0v */
SD_VOL_1_8_V = 3U,
/*!< card operation voltage around 31.8v */
/*!< card operation voltage around 1.8v */
};
#define SDMMC_DEFAULT_BLOCK_SIZE (512U)
@ -529,7 +529,7 @@ static inline int sdhc_map_r1_status(int status)
return sdhc_map_flags(sdhc_r1_flags, status);
}
/* Converts an eary stage idle mode R1 code into an error code */
/* Converts an early stage idle mode R1 code into an error code */
static inline int sdhc_map_r1_idle_status(int status)
{
if (status < 0) {

2
drivers/disk/sdmmc_spi.c
View file

@ -661,7 +661,7 @@ static int sdhc_spi_detect(const struct device *dev)
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], sys_get_be32(&buf[9]));
/* Initilisation complete */
/* Initialisation complete */
sdhc_spi_set_status(dev, DISK_STATUS_OK);
return 0;

12
drivers/disk/usdhc.c
View file

@ -762,7 +762,7 @@ static int usdhc_adma2_descriptor_cfg(
min_entries = ((data_size /
USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
}
/* calcucate the start entry for multiple descriptor mode,
/* calculate the start entry for multiple descriptor mode,
* ADMA engine is not stop, so update the descriptor
* data address and data size is enough
*/
@ -1537,7 +1537,7 @@ int usdhc_adjust_tuning_timing(USDHC_Type *base, uint32_t delay)
/* load the delay setting */
base->CLK_TUNE_CTRL_STATUS = clk_tune_ctrl;
/* check delat setting error */
/* check delay setting error */
if (base->CLK_TUNE_CTRL_STATUS &
(USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK |
USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK))
@ -1628,7 +1628,7 @@ static int usdhc_vol_switch(struct usdhc_priv *priv)
/*enable force clock on*/
usdhc_force_clk_on(base, true);
/* dealy 1ms,not exactly correct when use while */
/* delay 1ms,not exactly correct when use while */
usdhc_millsec_delay(20000U);
/*disable force clock on*/
usdhc_force_clk_on(base, false);
@ -1834,7 +1834,7 @@ uint32_t usdhc_set_sd_clk(USDHC_Type *base, uint32_t src_clk_hz, uint32_t sd_clk
}
}
} else {
/* in this situation , divsior and SDCLKFS
/* in this situation , divisor and SDCLKFS
* can generate same clock
* use SDCLKFS
*/
@ -1851,7 +1851,7 @@ uint32_t usdhc_set_sd_clk(USDHC_Type *base, uint32_t src_clk_hz, uint32_t sd_clk
} else {
/* in this condition , src_clk_hz = busClock_Hz, */
/* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the
* totoal divider = 2U
* total divider = 2U
*/
divisor = 0U;
prescaler = 0U;
@ -2676,7 +2676,7 @@ APP_SEND_OP_COND_AGAIN:
}
if (ret) {
LOG_ERR("USDHC bus device initalization failed!");
LOG_ERR("USDHC bus device initialization failed!");
}
return ret;