nordic: Remove the nRF54H20 Engineering B
The production version of the nRF54H20 SoC is now available, so remove the initial Engineering B (EngB) preview version. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
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16 changed files with 21 additions and 81 deletions
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@ -4,7 +4,7 @@
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config VPR_LAUNCHER
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bool "VPR launcher"
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default y
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depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_ENGB_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54H20_ENGB_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF9280_CPUPPR)
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depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF9280_CPUPPR)
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help
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Include VPR launcher in build.
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VPR launcher is a minimal sample built for an ARM core that starts given VPR core.
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@ -34,9 +34,6 @@ config SOC_NRF54H20_CPUAPP_COMMON
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config SOC_NRF54H20_CPUAPP
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select SOC_NRF54H20_CPUAPP_COMMON
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config SOC_NRF54H20_ENGB_CPUAPP
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select SOC_NRF54H20_CPUAPP_COMMON
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config SOC_NRF54H20_CPURAD_COMMON
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bool
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select ARM
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@ -61,19 +58,10 @@ config SOC_NRF54H20_CPURAD_COMMON
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config SOC_NRF54H20_CPURAD
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select SOC_NRF54H20_CPURAD_COMMON
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config SOC_NRF54H20_ENGB_CPURAD
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select SOC_NRF54H20_CPURAD_COMMON
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config SOC_NRF54H20_CPUPPR
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depends on RISCV_CORE_NORDIC_VPR
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config SOC_NRF54H20_ENGB_CPUPPR
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depends on RISCV_CORE_NORDIC_VPR
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config SOC_NRF54H20_CPUFLPR
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depends on RISCV_CORE_NORDIC_VPR
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config SOC_NRF54H20_ENGB_CPUFLPR
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depends on RISCV_CORE_NORDIC_VPR
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rsource "gpd/Kconfig"
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@ -3,7 +3,7 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54H20_CPUAPP || SOC_NRF54H20_ENGB_CPUAPP
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if SOC_NRF54H20_CPUAPP
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config NUM_IRQS
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default 471
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@ -14,4 +14,4 @@ config NRF_REGTOOL_GENERATE_UICR
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config SHELL_BACKEND_SERIAL
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default n if NRF_ETR_SHELL
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endif # SOC_NRF54H20_CPUAPP || SOC_NRF54H20_ENGB_CPUAPP
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endif # SOC_NRF54H20_CPUAPP
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@ -1,7 +1,7 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54H20_CPUFLPR || SOC_NRF54H20_ENGB_CPUFLPR
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if SOC_NRF54H20_CPUFLPR
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config NUM_IRQS
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default 496
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@ -10,4 +10,4 @@ config NUM_IRQS
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config ASSERT
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default n
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endif # SOC_NRF54H20_CPUFLPR || SOC_NRF54H20_ENGB_CPUFLPR
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endif # SOC_NRF54H20_CPUFLPR
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@ -1,7 +1,7 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54H20_CPUPPR || SOC_NRF54H20_ENGB_CPUPPR
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if SOC_NRF54H20_CPUPPR
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config NUM_IRQS
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default 496
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@ -13,4 +13,4 @@ config SYS_CLOCK_TICKS_PER_SEC
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config ASSERT
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default n
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endif # SOC_NRF54H20_CPUPPR || SOC_NRF54H20_ENGB_CPUPPR
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endif # SOC_NRF54H20_CPUPPR
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@ -3,7 +3,7 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54H20_CPURAD || SOC_NRF54H20_ENGB_CPURAD
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if SOC_NRF54H20_CPURAD
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config NUM_IRQS
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default 471
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@ -11,4 +11,4 @@ config NUM_IRQS
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config NRF_REGTOOL_GENERATE_UICR
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default y
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endif # SOC_NRF54H20_CPURAD || SOC_NRF54H20_ENGB_CPURAD
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endif # SOC_NRF54H20_CPURAD
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@ -9,59 +9,29 @@ config SOC_NRF54H20
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help
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nRF54H20
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config SOC_NRF54H20_ENGB
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bool
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select SOC_SERIES_NRF54HX
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help
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nRF54H20 (EngB)
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config SOC_NRF54H20_CPUAPP
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bool
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select SOC_NRF54H20
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help
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nRF54H20 CPUAPP
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config SOC_NRF54H20_ENGB_CPUAPP
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bool
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select SOC_NRF54H20_ENGB
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help
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nRF54H20 (EngB) CPUAPP
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config SOC_NRF54H20_CPURAD
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bool
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select SOC_NRF54H20
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help
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nRF54H20 CPURAD
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config SOC_NRF54H20_ENGB_CPURAD
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bool
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select SOC_NRF54H20_ENGB
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help
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nRF54H20 (EngB) CPURAD
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config SOC_NRF54H20_CPUPPR
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bool
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select SOC_NRF54H20
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help
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nRF54H20 CPUPPR
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config SOC_NRF54H20_ENGB_CPUPPR
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bool
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select SOC_NRF54H20_ENGB
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help
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nRF54H20 (EngB) CPUPPR
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config SOC_NRF54H20_CPUFLPR
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bool
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select SOC_NRF54H20
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help
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nRF54H20 CPUFLPR
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config SOC_NRF54H20_ENGB_CPUFLPR
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bool
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select SOC_NRF54H20_ENGB
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help
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nRF54H20 (EngB) CPUFLPR
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config SOC
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default "nrf54h20" if SOC_NRF54H20 || SOC_NRF54H20_ENGB
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default "nrf54h20" if SOC_NRF54H20
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@ -6,7 +6,6 @@ config SOC_NRF54H20_GPD
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imply NRFS
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imply NRFS_GDPWR_SERVICE_ENABLED
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select ONOFF
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default y if SOC_NRF54H20_CPUAPP || SOC_NRF54H20_ENGB_CPUAPP || \
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SOC_NRF54H20_CPURAD || SOC_NRF54H20_ENGB_CPURAD
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default y if SOC_NRF54H20_CPUAPP || SOC_NRF54H20_CPURAD
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help
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This option enables the Global Power Domain service.
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@ -9,7 +9,7 @@
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#include <soc_nrf_common.h>
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#if defined(CONFIG_SOC_NRF54H20_CPUAPP) || defined(CONFIG_SOC_NRF54H20_ENGB_CPUAPP)
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#if defined(CONFIG_SOC_NRF54H20_CPUAPP)
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#define RAMBLOCK_CONTROL_BIT_ICACHE MEMCONF_POWER_CONTROL_MEM1_Pos
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#define RAMBLOCK_CONTROL_BIT_DCACHE MEMCONF_POWER_CONTROL_MEM2_Pos
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#define RAMBLOCK_POWER_ID 0
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#define RAMBLOCK_RET_MASK (MEMCONF_POWER_RET_MEM0_Msk)
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#define RAMBLOCK_RET_BIT_ICACHE MEMCONF_POWER_RET_MEM1_Pos
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#define RAMBLOCK_RET_BIT_DCACHE MEMCONF_POWER_RET_MEM2_Pos
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#elif defined(CONFIG_SOC_NRF54H20_CPURAD) || defined(CONFIG_SOC_NRF54H20_ENGB_CPURAD)
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#elif defined(CONFIG_SOC_NRF54H20_CPURAD)
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#define RAMBLOCK_CONTROL_BIT_ICACHE MEMCONF_POWER_CONTROL_MEM6_Pos
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#define RAMBLOCK_CONTROL_BIT_DCACHE MEMCONF_POWER_CONTROL_MEM7_Pos
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#define RAMBLOCK_POWER_ID 0
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