soc: esp32s2: refactor cache and bss initialization
- refactors cache initialization functions by moving it from soc.c and placing it in soc_cache.c - moves SPIRAM's bss zeroing before SPIRAM initialization Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This commit is contained in:
Glauber Maroto Ferreira
Anas Nashif
parent
c5857dc0cd
commit
963a707ae4
4 changed files with 105 additions and 60 deletions
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@ -2,4 +2,5 @@
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zephyr_sources(
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soc.c
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soc_cache.c
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)
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@ -59,32 +59,7 @@ void __attribute__((section(".iram1"))) __start(void)
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* Configure the mode of instruction cache :
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* cache size, cache associated ways, cache line size.
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*/
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_16KB;
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#endif
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cache_ways = CACHE_4WAYS_ASSOC;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#else
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cache_line_size = CACHE_LINE_SIZE_32B;
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#endif
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esp_rom_Cache_Suspend_ICache();
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esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
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esp_rom_Cache_Invalidate_ICache_All();
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esp_rom_Cache_Resume_ICache(0);
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esp_config_instruction_cache_mode();
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/*
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* If we need use SPIRAM, we should use data cache, or if we want to
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@ -93,36 +68,7 @@ void __attribute__((section(".iram1"))) __start(void)
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* line size.
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* Enable data cache, so if we don't use SPIRAM, it just works.
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*/
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
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CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_16KB;
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#endif
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#else
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
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cache_size = CACHE_SIZE_16KB;
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#endif
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#endif
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cache_ways = CACHE_4WAYS_ASSOC;
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#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#else
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cache_line_size = CACHE_LINE_SIZE_32B;
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#endif
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esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
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esp_rom_Cache_Invalidate_DCache_All();
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esp_config_data_cache_mode();
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esp_rom_Cache_Enable_DCache(0);
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#if !CONFIG_BOOTLOADER_ESP_IDF
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@ -165,6 +111,11 @@ void __attribute__((section(".iram1"))) __start(void)
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#endif
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#if CONFIG_ESP_SPIRAM
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memset(&_ext_ram_bss_start,
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0,
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(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
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esp_err_t err = esp_spiram_init();
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if (err != ESP_OK) {
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@ -177,10 +128,7 @@ void __attribute__((section(".iram1"))) __start(void)
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abort();
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}
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memset(&_ext_ram_bss_start,
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0,
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(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
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#endif
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#endif /* CONFIG_ESP_SPIRAM */
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/* Scheduler is not started at this point. Hence, guard functions
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* must be initialized after esp_spiram_init_cache which internally
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@ -62,4 +62,8 @@ extern uint8_t g_rom_spiflash_dummy_len_plus[];
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extern uint32_t esp_rom_g_ticks_per_us_pro;
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/* cache initialization functions */
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void IRAM_ATTR esp_config_instruction_cache_mode(void);
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void IRAM_ATTR esp_config_data_cache_mode(void);
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#endif /* __SOC_H__ */
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92
soc/xtensa/esp32s2/soc_cache.c
Normal file
92
soc/xtensa/esp32s2/soc_cache.c
Normal file
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@ -0,0 +1,92 @@
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc.h"
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/*
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* Instruction Cache definitions
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*/
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#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB)
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#define ESP32S2_ICACHE_SIZE CACHE_SIZE_8KB
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#else
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#define ESP32S2_ICACHE_SIZE CACHE_SIZE_16KB
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#endif
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#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B)
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#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#else
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#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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/*
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* Data Cache definitions
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*/
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#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB)
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#define ESP32S2_DCACHE_SIZE CACHE_SIZE_8KB
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#else
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#define ESP32S2_DCACHE_SIZE CACHE_SIZE_16KB
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#endif
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#if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B)
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#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#else
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#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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void IRAM_ATTR esp_config_instruction_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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#endif
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cache_size = ESP32S2_ICACHE_SIZE;
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cache_ways = CACHE_4WAYS_ASSOC;
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cache_line_size = ESP32S2_ICACHE_LINE_SIZE;
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esp_rom_Cache_Suspend_ICache();
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esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
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esp_rom_Cache_Invalidate_ICache_All();
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esp_rom_Cache_Resume_ICache(0);
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}
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void IRAM_ATTR esp_config_data_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
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CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
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#endif
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#else
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
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#endif
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#endif
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cache_size = ESP32S2_DCACHE_SIZE;
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cache_ways = CACHE_4WAYS_ASSOC;
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cache_line_size = ESP32S2_DCACHE_LINE_SIZE;
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esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
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esp_rom_Cache_Invalidate_DCache_All();
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}
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