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interrupt: Convert RISC-V plic to use multi-level irq support

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Utilize the multi-level irq infrastructure and replace custom handling
for PLIC on riscv-privilege SoCs.  The old code offset IRQs in drivers
and various places with RISCV_MAX_GENERIC_IRQ.  Instead utilize Zephyr's
encoded IRQ and replace offsets in drivers with the IRQ define from DTS.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-08-08 23:01:37 -05:00 • committed by Kumar Gala
commit 95f78bcacf
10 changed files with 121 additions and 67 deletions
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45
soc/riscv/riscv-privilege/common/soc_common_irq.c
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@ -11,12 +11,30 @@
*/
#include <irq.h>
/**
* @brief Get an IRQ's level
* @param irq The IRQ number in the Zephyr irq.h numbering system
* @return IRQ level, either 1 or 2
*/
static inline unsigned int _irq_level(unsigned int irq)
{
return ((irq >> 8) & 0xff) == 0U ? 1 : 2;
}
static inline unsigned int _level2_irq(unsigned int irq)
{
return (irq >> 8) - 1;
}
void z_arch_irq_enable(unsigned int irq)
{
u32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ) {
unsigned int level = _irq_level(irq);
if (level == 2) {
irq = _level2_irq(irq);
riscv_plic_irq_enable(irq);
return;
}
@ -36,7 +54,10 @@ void z_arch_irq_disable(unsigned int irq)
u32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ) {
unsigned int level = _irq_level(irq);
if (level == 2) {
irq = _level2_irq(irq);
riscv_plic_irq_disable(irq);
return;
}
@ -51,13 +72,31 @@ void z_arch_irq_disable(unsigned int irq)
: "r" (1 << irq));
};
void z_arch_irq_priority_set(unsigned int irq, unsigned int prio)
{
#if defined(CONFIG_RISCV_HAS_PLIC)
unsigned int level = _irq_level(irq);
if (level == 2) {
irq = _level2_irq(irq);
riscv_plic_set_priority(irq, prio);
}
#endif
return ;
}
int z_arch_irq_is_enabled(unsigned int irq)
{
u32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ)
unsigned int level = _irq_level(irq);
if (level == 2) {
irq = _level2_irq(irq);
return riscv_plic_irq_is_enabled(irq);
}
#endif
__asm__ volatile ("csrr %0, mie" : "=r" (mie));