michaelh/zephyr
1
0
Fork 0
Code Releases Activity

interrupt: Convert RISC-V plic to use multi-level irq support

Browse source 
Utilize the multi-level irq infrastructure and replace custom handling
for PLIC on riscv-privilege SoCs.  The old code offset IRQs in drivers
and various places with RISCV_MAX_GENERIC_IRQ.  Instead utilize Zephyr's
encoded IRQ and replace offsets in drivers with the IRQ define from DTS.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-08-08 23:01:37 -05:00 • committed by Kumar Gala
commit 95f78bcacf
10 changed files with 121 additions and 67 deletions
Download patch file Download diff file Expand all files Collapse all files

7
drivers/gpio/gpio_sifive.c
View file

@ -68,8 +68,7 @@ static void gpio_sifive_irq_handler(void *arg)
int pin_mask;
/* Get the pin number generating the interrupt */
pin_mask = 1 << (riscv_plic_get_irq() -
(cfg->gpio_irq_base - RISCV_MAX_GENERIC_IRQ));
pin_mask = 1 << (riscv_plic_get_irq() - cfg->gpio_irq_base);
/* Call the corresponding callback registered for the pin */
gpio_fire_callbacks(&data->cb, dev, pin_mask);
@ -375,7 +374,7 @@ static void gpio_sifive_cfg_0(void);
static const struct gpio_sifive_config gpio_sifive_config0 = {
.gpio_base_addr = DT_INST_0_SIFIVE_GPIO0_BASE_ADDRESS,
.gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_INST_0_SIFIVE_GPIO0_IRQ_0,
.gpio_irq_base = DT_INST_0_SIFIVE_GPIO0_IRQ_0,
.gpio_cfg_func = gpio_sifive_cfg_0,
};
@ -388,7 +387,7 @@ DEVICE_AND_API_INIT(gpio_sifive_0, DT_INST_0_SIFIVE_GPIO0_LABEL,
&gpio_sifive_driver);
#define IRQ_INIT(n) \
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_INST_0_SIFIVE_GPIO0_IRQ_##n, \
IRQ_CONNECT(DT_INST_0_SIFIVE_GPIO0_IRQ_##n, \
CONFIG_GPIO_SIFIVE_##n##_PRIORITY, \
gpio_sifive_irq_handler, \
DEVICE_GET(gpio_sifive_0), \