soc: LPC55S69: Add USB support

1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
   buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

boards/arm/lpcxpresso55s69/doc/index.rst

@@ -80,6 +80,8 @@ features:
 +-----------+------------+-------------------------------------+
 | HWINFO    | on-chip    | Unique device serial number         |
 +-----------+------------+-------------------------------------+
+| USB       | on-chip    | USB device                          |
++-----------+------------+-------------------------------------+
 
 Targets available
 ==================

boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts

@@ -105,3 +105,7 @@
 &mailbox0 {
 	status = "okay";
 };
+
+zephyr_udc0: &usbhs {
+	status = "okay";
+};

boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml

@@ -22,4 +22,5 @@ supported:
   - gpio
   - i2c
   - spi
+  - usb_device
   - watchdog

boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts

@@ -103,3 +103,7 @@
 	dma-channels = <20>;
 	status = "okay";
 };
+
+zephyr_udc0: &usbhs {
+	status = "okay";
+};

soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt

@@ -12,6 +12,9 @@ zephyr_library_include_directories(
   ${ZEPHYR_BASE}/arch/${ARCH}/include
   )
 
+zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
+  SECTIONS usb.ld)
+
 if (CONFIG_SECOND_CORE_MCUX)
   set(gen_dir ${ZEPHYR_BINARY_DIR}/include/generated/)
   string(CONFIGURE ${CONFIG_SECOND_IMAGE_MCUX} second_core_image)

soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0

@@ -37,4 +37,12 @@ config DMA_MCUX_LPC
 	default y
 	depends on DMA
 
+config USB_MCUX
+	default y
+	depends on USB_DEVICE_DRIVER
+
+choice USB_MCUX_CONTROLLER_TYPE
+	default USB_DC_NXP_LPCIP3511
+endchoice
+
 endif # SOC_LPC55S69_CPU0

soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc

@@ -41,6 +41,8 @@ config SOC_LPC55S69_CPU0
 	select HAS_MCUX_IAP
 	select HAS_MCUX_LPADC
 	select HAS_MCUX_LPC_DMA
+	select HAS_MCUX_USB_LPCIP3511
+	select USB_DEDICATED_MEMORY if USB_DEVICE_DRIVER
 
 config SOC_LPC55S69_CPU1
 	bool "SOC_LPC55S69 M33 [CPU 1]"
@@ -87,6 +89,9 @@ config SECOND_IMAGE_MCUX
 	  This points to the image file for the the binary code that will be
 	  used by the second core.
 
+config USB_DEDICATED_MEMORY
+	bool "Dedicated memory for USB transfer buffer and controller operation buffers"
+
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
 

soc/arm/nxp_lpc/lpc55xxx/soc.c

@@ -25,6 +25,10 @@
 #include <fsl_common.h>
 #include <fsl_device_registers.h>
 #include <fsl_pint.h>
+#if CONFIG_USB_DC_NXP_LPCIP3511
+#include "usb_phy.h"
+#include "usb_dc_mcux.h"
+#endif
 
 /**
  *
@@ -95,6 +99,31 @@ static ALWAYS_INLINE void clock_init(void)
 	RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn);
 #endif
 
+#if CONFIG_USB_DC_NXP_LPCIP3511
+	/* enable usb1 host clock */
+	CLOCK_EnableClock(kCLOCK_Usbh1);
+	/* Put PHY powerdown under software control */
+	*((uint32_t *)(USBHSH_BASE + 0x50)) = USBHSH_PORTMODE_SW_PDCOM_MASK;
+	/*
+	 * According to reference mannual, device mode setting has to be set by
+	 * access usb host register
+	 */
+	*((uint32_t *)(USBHSH_BASE + 0x50)) |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+	/* enable usb1 host clock */
+	CLOCK_DisableClock(kCLOCK_Usbh1);
+
+	/* enable USB IP clock */
+	CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, CLK_CLK_IN);
+	CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
+	USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_CLK_IN, NULL);
+#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
+	for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) {
+		((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U;
+	}
+#endif
+
+#endif
+
 #endif /* CONFIG_SOC_LPC55S69_CPU0 */
 }
 

soc/arm/nxp_lpc/lpc55xxx/usb.ld

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+GROUP_START(USB_BDT)
+
+	SECTION_PROLOGUE(_USB_BDT_SECTION_NAME,(NOLOAD),)
+	{
+		. = ALIGN(512);
+		*(m_usb_bdt)
+	} GROUP_LINK_IN(SRAM4)
+
+GROUP_END(USB_BDT)
+
+GROUP_START(USB_GLOBAL)
+
+	SECTION_PROLOGUE(_USB_GLOBAL_SECTION_NAME,(NOLOAD),)
+	{
+		*(m_usb_global)
+	} GROUP_LINK_IN(SRAM4)
+
+GROUP_END(USB_GLOBAL)