diff --git a/soc/arm/nordic_nrf/nrf52/CMakeLists.txt b/soc/arm/nordic_nrf/nrf52/CMakeLists.txt
index 8aaf65d1655..f66c9a0be34 100644
--- a/soc/arm/nordic_nrf/nrf52/CMakeLists.txt
+++ b/soc/arm/nordic_nrf/nrf52/CMakeLists.txt
@@ -10,10 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_SYS_POWER_MANAGEMENT
   power.c
   )
 
-zephyr_library_sources_ifdef(CONFIG_ARM_MPU
-  mpu_regions.c
-  )
-
 zephyr_library_include_directories(
   ${ZEPHYR_BASE}/kernel/include
   ${ZEPHYR_BASE}/arch/arm/include
diff --git a/soc/arm/nordic_nrf/nrf52/mpu_mem_cfg.h b/soc/arm/nordic_nrf/nrf52/mpu_mem_cfg.h
deleted file mode 100644
index a3242c5d549..00000000000
--- a/soc/arm/nordic_nrf/nrf52/mpu_mem_cfg.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2017 Linaro Limited.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _NRF52X_MPU_MEM_CFG_H_
-#define _NRF52X_MPU_MEM_CFG_H_
-
-#include <arch/arm/cortex_m/mpu/arm_mpu.h>
-
-/* Flash Region Definitions */
-#if CONFIG_FLASH_SIZE == 64
-#define REGION_FLASH_SIZE REGION_64K
-#elif CONFIG_FLASH_SIZE == 128
-#define REGION_FLASH_SIZE REGION_128K
-#elif CONFIG_FLASH_SIZE == 192
-/* Use the next power-of-two size, to save one MPU region. */
-#define REGION_FLASH_SIZE    REGION_256K
-#elif CONFIG_FLASH_SIZE == 256
-#define REGION_FLASH_SIZE REGION_256K
-#elif CONFIG_FLASH_SIZE == 512
-#define REGION_FLASH_SIZE REGION_512K
-#elif CONFIG_FLASH_SIZE == 1024
-#define REGION_FLASH_SIZE REGION_1M
-#elif CONFIG_FLASH_SIZE == 2048
-#define REGION_FLASH_SIZE REGION_2M
-#else
-#error "Unsupported configuration"
-#endif
-
-/* SRAM Region Definitions */
-#if CONFIG_SRAM_SIZE == 24
-#define REGION_SRAM_0_SIZE  REGION_32K
-/* Use the next power-of-two size, to save one MPU region. */
-#elif CONFIG_SRAM_SIZE == 32
-#define REGION_SRAM_0_SIZE REGION_32K
-#elif CONFIG_SRAM_SIZE == 64
-#define REGION_SRAM_0_SIZE REGION_64K
-#elif CONFIG_SRAM_SIZE == 128
-#define REGION_SRAM_0_SIZE REGION_128K
-#elif CONFIG_SRAM_SIZE == 256
-#define REGION_SRAM_0_SIZE REGION_256K
-#else
-#error "Unsupported configuration"
-#endif
-
-#endif /* _NRF52X_MPU_MEM_CFG_H_ */
diff --git a/soc/arm/nordic_nrf/nrf52/mpu_regions.c b/soc/arm/nordic_nrf/nrf52/mpu_regions.c
deleted file mode 100644
index bc1b2126059..00000000000
--- a/soc/arm/nordic_nrf/nrf52/mpu_regions.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2017 Linaro Limited.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <sys/slist.h>
-#include <arch/arm/cortex_m/mpu/arm_mpu.h>
-
-#include "mpu_mem_cfg.h"
-
-static const struct arm_mpu_region mpu_regions[] = {
-	/* Region 0 */
-	MPU_REGION_ENTRY("FLASH_0",
-			 CONFIG_FLASH_BASE_ADDRESS,
-			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
-#if defined(REGION_FLASH_1_SIZE)
-	MPU_REGION_ENTRY("FLASH_1",
-			 REGION_FLASH_1_START,
-			 REGION_FLASH_ATTR(REGION_FLASH_1_SIZE)),
-#endif /* REGION_FLASH_1_SIZE */
-	/* Region 1 */
-	MPU_REGION_ENTRY("SRAM_0",
-			 CONFIG_SRAM_BASE_ADDRESS,
-			 REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
-
-#if defined(REGION_SRAM_1_SIZE)
-	MPU_REGION_ENTRY("SRAM_1",
-			 REGION_SRAM_1_START,
-			 REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
-#endif /* REGION_SRAM_1_SIZE */
-};
-
-const struct arm_mpu_config mpu_config = {
-	.num_regions = ARRAY_SIZE(mpu_regions),
-	.mpu_regions = mpu_regions,
-};
diff --git a/soc/arm/nordic_nrf/nrf53/CMakeLists.txt b/soc/arm/nordic_nrf/nrf53/CMakeLists.txt
index f9e41e29976..332416ba43b 100644
--- a/soc/arm/nordic_nrf/nrf53/CMakeLists.txt
+++ b/soc/arm/nordic_nrf/nrf53/CMakeLists.txt
@@ -3,5 +3,3 @@
 zephyr_sources(
   soc.c
   )
-
-zephyr_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)
diff --git a/soc/arm/nordic_nrf/nrf53/mpu_regions.c b/soc/arm/nordic_nrf/nrf53/mpu_regions.c
deleted file mode 100644
index b245c260a3f..00000000000
--- a/soc/arm/nordic_nrf/nrf53/mpu_regions.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2017 Linaro Limited.
- * Copyright (c) 2019 Nordic Semiconductor ASA.
- *
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <misc/slist.h>
-#include <arch/arm/cortex_m/mpu/arm_mpu.h>
-
-
-static const struct arm_mpu_region mpu_regions[] = {
-	/* Region 0 */
-	MPU_REGION_ENTRY("FLASH_0",
-		CONFIG_FLASH_BASE_ADDRESS,
-		REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \
-			CONFIG_FLASH_SIZE * 1024)),
-	/* Region 1 */
-	MPU_REGION_ENTRY("SRAM_0",
-		CONFIG_SRAM_BASE_ADDRESS,
-		REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \
-			CONFIG_SRAM_SIZE * 1024)),
-};
-
-const struct arm_mpu_config mpu_config = {
-	.num_regions = ARRAY_SIZE(mpu_regions),
-	.mpu_regions = mpu_regions,
-};
diff --git a/soc/arm/nordic_nrf/nrf91/CMakeLists.txt b/soc/arm/nordic_nrf/nrf91/CMakeLists.txt
index f9e41e29976..332416ba43b 100644
--- a/soc/arm/nordic_nrf/nrf91/CMakeLists.txt
+++ b/soc/arm/nordic_nrf/nrf91/CMakeLists.txt
@@ -3,5 +3,3 @@
 zephyr_sources(
   soc.c
   )
-
-zephyr_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)
diff --git a/soc/arm/nordic_nrf/nrf91/mpu_regions.c b/soc/arm/nordic_nrf/nrf91/mpu_regions.c
deleted file mode 100644
index 5a76e172447..00000000000
--- a/soc/arm/nordic_nrf/nrf91/mpu_regions.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2017 Linaro Limited.
- * Copyright (c) 2018 Nordic Semiconductor ASA.
- *
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <sys/slist.h>
-#include <arch/arm/cortex_m/mpu/arm_mpu.h>
-
-
-static const struct arm_mpu_region mpu_regions[] = {
-	/* Region 0 */
-	MPU_REGION_ENTRY("FLASH_0",
-		CONFIG_FLASH_BASE_ADDRESS,
-		REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \
-			CONFIG_FLASH_SIZE * 1024)),
-	/* Region 1 */
-	MPU_REGION_ENTRY("SRAM_0",
-		CONFIG_SRAM_BASE_ADDRESS,
-		REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \
-			CONFIG_SRAM_SIZE * 1024)),
-};
-
-const struct arm_mpu_config mpu_config = {
-	.num_regions = ARRAY_SIZE(mpu_regions),
-	.mpu_regions = mpu_regions,
-};