diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
new file mode 100644
index 00000000000..c80ca2147df
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
@@ -0,0 +1,29 @@
+# Kconfig.defconfig.series - ST Microelectronics STM32F4 MCU line
+#
+# Copyright (c) 2016 Linaro Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_SERIES_STM32F4X
+
+source "arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f4*"
+
+config SOC_SERIES
+	default stm32f4
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 4
+
+endif # SOC_SERIES_STM32F4X
diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f401re b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f401re
new file mode 100644
index 00000000000..024f1eb060d
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f401re
@@ -0,0 +1,34 @@
+# Kconfig - ST STM32F401RE MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_STM32F401RE
+
+config SOC
+	string
+	default stm32f401re
+
+config SRAM_SIZE
+	default 96
+
+config FLASH_SIZE
+	default 512
+
+config NUM_IRQS
+	int
+	default 85
+
+endif # SOC_STM32F401RE
diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.series b/arch/arm/soc/st_stm32/stm32f4/Kconfig.series
new file mode 100644
index 00000000000..b385ef334ce
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.series
@@ -0,0 +1,25 @@
+# Kconfig - ST Microelectronics STM32F1 MCU series
+#
+# Copyright (c) 2016 Linaro Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_SERIES_STM32F4X
+	bool "STM32F4x Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	help
+	 Enable support for STM32F4 MCU series
diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
new file mode 100644
index 00000000000..e002c748491
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
@@ -0,0 +1,25 @@
+# Kconfig.soc - ST Microelectronics STM32F4 MCU line
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+prompt "STM32F4x MCU Selection"
+depends on SOC_SERIES_STM32F4X
+
+config SOC_STM32F401RE
+	bool "STM32F401RE"
+
+endchoice
diff --git a/arch/arm/soc/st_stm32/stm32f4/Makefile b/arch/arm/soc/st_stm32/stm32f4/Makefile
new file mode 100644
index 00000000000..fd8d5a50505
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/Makefile
@@ -0,0 +1,4 @@
+obj-y += soc.o
+
+zephyr: $(KERNEL_HEX_NAME)
+all: $(KERNEL_HEX_NAME)
diff --git a/arch/arm/soc/st_stm32/stm32f4/linker.ld b/arch/arm/soc/st_stm32/stm32f4/linker.ld
new file mode 100644
index 00000000000..220d80cc101
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/linker.ld
@@ -0,0 +1,19 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>
diff --git a/arch/arm/soc/st_stm32/stm32f4/soc.c b/arch/arm/soc/st_stm32/stm32f4/soc.c
new file mode 100644
index 00000000000..a6b453d3576
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/soc.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32F4 processor
+ */
+
+#include <nanokernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <arch/cpu.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int st_stm32f4_init(struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	/* Setup the vector table offset register (VTOR),
+	 * which is located at the beginning of flash area.
+	 */
+	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
+
+	/* Clear all faults */
+	_ScbMemFaultAllFaultsReset();
+	_ScbBusFaultAllFaultsReset();
+	_ScbUsageFaultAllFaultsReset();
+
+	_ScbHardFaultAllFaultsReset();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(st_stm32f4_init, PRIMARY, 0);
diff --git a/arch/arm/soc/st_stm32/stm32f4/soc.h b/arch/arm/soc/st_stm32/stm32f4/soc.h
new file mode 100644
index 00000000000..e58307b939f
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/soc.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file SoC configuration macros for the ST STM32F4 family processors.
+ *
+ * Based on reference manual:
+ *   RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 2.3: Memory Map
+ */
+
+#ifndef _STM32F4_SOC_H_
+#define _STM32F4_SOC_H_
+
+/* peripherals start address */
+#define PERIPH_BASE           0x40000000
+
+/* use naming consistent with STMF4 Peripherals Library */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+
+/* UART */
+#define USART1_ADDR           (APB2PERIPH_BASE + 0x1000)
+#define USART2_ADDR           (APB1PERIPH_BASE + 0x4400)
+#define USART6_ADDR           (APB2PERIPH_BASE + 0x1400)
+
+/* Reset and Clock Control */
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
+
+#define GPIO_REG_SIZE         0x400
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
+
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+/* EXTI */
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
+
+/* IWDG */
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+
+/* FLASH */
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
+
+#ifndef _ASMLANGUAGE
+
+#include <device.h>
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#include "soc_irq.h"
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F4_SOC_H_ */
diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_irq.h b/arch/arm/soc/st_stm32/stm32f4/soc_irq.h
new file mode 100644
index 00000000000..2c77a3d9361
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/soc_irq.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Interrupt numbers for STM32F4 family processors.
+ *
+ * Based on reference manual:
+ *   RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
+ *   advanced ARM-based 32-bit MCUs
+ *
+ * Chapter 10.1.3: Interrupt and exception vectors
+ */
+
+
+#ifndef _STM32F4_SOC_IRQ_H_
+#define _STM32F4_SOC_IRQ_H_
+
+#define STM32F4_IRQ_WWDG		0
+#define STM32F4_IRQ_PVD			1
+#define STM32F4_IRQ_EXTI16		STM32F4_IRQ_PVD
+#define STM32F4_IRQ_TAMP_STAMP		2
+#define STM32F4_IRQ_EXTI21		STM32F4_IRQ_TAMP_STAMP
+#define STM32F4_IRQ_RTC_WKUP		3
+#define STM32F4_IRQ_EXTI22		STM32F4_IRQ_RTC_WKUP
+#define STM32F4_IRQ_FLASH		4
+#define STM32F4_IRQ_RCC			5
+#define STM32F4_IRQ_EXTI0		6
+#define STM32F4_IRQ_EXTI1		7
+#define STM32F4_IRQ_EXTI2		8
+#define STM32F4_IRQ_EXTI3		9
+#define STM32F4_IRQ_EXTI4		10
+#define STM32F4_IRQ_DMA1_STREAM0	11
+#define STM32F4_IRQ_DMA1_STREAM1	12
+#define STM32F4_IRQ_DMA1_STREAM2	13
+#define STM32F4_IRQ_DMA1_STREAM3	14
+#define STM32F4_IRQ_DMA1_STREAM4	15
+#define STM32F4_IRQ_DMA1_STREAM5	16
+#define STM32F4_IRQ_DMA1_STREAM6	17
+#define STM32F4_IRQ_ADC			18
+#define STM32F4_IRQ_CAN1_TX		19
+#define STM32F4_IRQ_CAN1_RX0		20
+#define STM32F4_IRQ_CAN1_RX1		21
+#define STM32F4_IRQ_CAN1_SCE		22
+#define STM32F4_IRQ_EXTI9_5		23
+#define STM32F4_IRQ_TIM1_BRK_TIM9	24
+#define STM32F4_IRQ_TIM1_UP_TIM10	25
+#define STM32F4_IRQ_TIM1_TRG_COM_TIM11	26
+#define STM32F4_IRQ_TIM1_CC		27
+#define STM32F4_IRQ_TIM2		28
+#define STM32F4_IRQ_TIM3		29
+#define STM32F4_IRQ_TIM4		30
+#define STM32F4_IRQ_I2C1_EV		31
+#define STM32F4_IRQ_I2C1_ER		32
+#define STM32F4_IRQ_I2C2_EV		33
+#define STM32F4_IRQ_I2C2_ER		34
+#define STM32F4_IRQ_SPI1		35
+#define STM32F4_IRQ_SPI2		36
+#define STM32F4_IRQ_USART1		37
+#define STM32F4_IRQ_USART2		38
+#define STM32F4_IRQ_USART3		39
+#define STM32F4_IRQ_EXTI15_10		40
+#define STM32F4_IRQ_RTC_ALARM		41
+#define STM32F4_IRQ_EXTI17		STM32F4_IRQ_RTC_ALARM
+#define STM32F4_IRQ_OTG_FS_WKUP		42
+#define STM32F4_IRQ_EXTI18		STM32F4_IRQ_OTG_FS_WKUP
+#define STM32F4_IRQ_TIM8_BRK_TIM12	43
+#define STM32F4_IRQ_TIM8_UP_TIM12	44
+#define STM32F4_IRQ_TIM8_TRG_COM_TIM14	45
+#define STM32F4_IRQ_TIM8_CC		46
+#define STM32F4_IRQ_DMA1_STREAM7	47
+#define STM32F4_IRQ_FSMC		48
+#define STM32F4_IRQ_SDIO		49
+#define STM32F4_IRQ_TIM5		50
+#define STM32F4_IRQ_SPI3		51
+#define STM32F4_IRQ_UART4		52
+#define STM32F4_IRQ_UART5		53
+#define STM32F4_IRQ_TIM6_DAC		54
+#define STM32F4_IRQ_TIM7		55
+#define STM32F4_IRQ_DMA2_STREAM0	56
+#define STM32F4_IRQ_DMA2_STREAM1	57
+#define STM32F4_IRQ_DMA2_STREAM2	58
+#define STM32F4_IRQ_DMA2_STREAM3	59
+#define STM32F4_IRQ_DMA2_STREAM4	60
+#define STM32F4_IRQ_ETH			61
+#define STM32F4_IRQ_ETH_WKUP		62
+#define STM32F4_IRQ_CAN2_TX		63
+#define STM32F4_IRQ_CAN2_RX0		64
+#define STM32F4_IRQ_CAN2_RX1		65
+#define STM32F4_IRQ_CAN2_SCE		66
+#define STM32F4_IRQ_OTG_FS		67
+#define STM32F4_IRQ_DMA2_STREAM5	68
+#define STM32F4_IRQ_DMA2_STREAM6	69
+#define STM32F4_IRQ_DMA2_STREAM7	70
+#define STM32F4_IRQ_USART6		71
+#define STM32F4_IRQ_I2C3_EV		72
+#define STM32F4_IRQ_I2C3_ER		73
+#define STM32F4_IRQ_OTG_HS_EP1_OUT	74
+#define STM32F4_IRQ_OTG_HS_EP1_IN	75
+#define STM32F4_IRQ_OTG_HS_WKUP		76
+#define STM32F4_IRQ_OTG_HS		77
+#define STM32F4_IRQ_DCMI		78
+#define STM32F4_IRQ_CRYP		79
+#define STM32F4_IRQ_HASH_RNG		80
+#define STM32F4_IRQ_FPU			81
+#define STM32F4_IRQ_UART7		82
+#define STM32F4_IRQ_UART8		83
+#define STM32F4_IRQ_SPI4		84
+#define STM32F4_IRQ_SPI5		85
+#define STM32F4_IRQ_SPI6		86
+#define STM32F4_IRQ_SAI1		87
+#define STM32F4_IRQ_LTDC		88
+#define STM32F4_IRQ_LTDC_ER		89
+#define STM32F4_IRQ_DMA2D		90
+#define STM32F4_IRQ_QUADSPI		91
+#define STM32F4_IRQ_DSI			92
+#define STM32F4_IRQ_CEC			93
+#define STM32F4_IRQ_SPDIF_RX		94
+#define STM32F4_IRQ_FMPI2C1_EV		95
+#define STM32F4_IRQ_FMPI2C1_ER		96
+#define STM32F4_IRQ_LPTIM1		97
+
+#endif	/* _STM32F4_SOC_IRQ_H_ */
diff --git a/drivers/interrupt_controller/Kconfig.stm32 b/drivers/interrupt_controller/Kconfig.stm32
index c30235d382e..c2382ada7aa 100644
--- a/drivers/interrupt_controller/Kconfig.stm32
+++ b/drivers/interrupt_controller/Kconfig.stm32
@@ -72,4 +72,44 @@ config EXTI_STM32_EXTI15_10_IRQ_PRI
 	help
 	 IRQ priority of EXTI15:10 interrupt
 
+config EXTI_STM32_EXTI16_IRQ_PRI
+	int "EXTI16 IRQ priority"
+	depends on EXTI_STM32
+	depends on SOC_SERIES_STM32F4X
+	default 0
+	help
+	 IRQ priority of EXTI16 interrupt
+
+config EXTI_STM32_EXTI17_IRQ_PRI
+	int "EXTI17 IRQ priority"
+	depends on EXTI_STM32
+	depends on SOC_SERIES_STM32F4X
+	default 0
+	help
+	 IRQ priority of EXTI17 interrupt
+
+config EXTI_STM32_EXTI18_IRQ_PRI
+	int "EXTI18 IRQ priority"
+	depends on EXTI_STM32
+	depends on SOC_SERIES_STM32F4X
+	default 0
+	help
+	 IRQ priority of EXTI18 interrupt
+
+config EXTI_STM32_EXTI21_IRQ_PRI
+	int "EXTI21 IRQ priority"
+	depends on EXTI_STM32
+	depends on SOC_SERIES_STM32F4X
+	default 0
+	help
+	 IRQ priority of EXTI21 interrupt
+
+config EXTI_STM32_EXTI22_IRQ_PRI
+	int "EXTI22 IRQ priority"
+	depends on EXTI_STM32
+	depends on SOC_SERIES_STM32F4X
+	default 0
+	help
+	 IRQ priority of EXTI22 interrupt
+
 endif # SOC_FAMILY_STM32
diff --git a/drivers/interrupt_controller/exti_stm32.c b/drivers/interrupt_controller/exti_stm32.c
index d55f933ccda..6409f93817d 100644
--- a/drivers/interrupt_controller/exti_stm32.c
+++ b/drivers/interrupt_controller/exti_stm32.c
@@ -17,9 +17,12 @@
 /**
  * @brief Driver for External interrupt/event controller in STM32 MCUs
  *
- * Based on reference manual:
- *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
- *   advanced ARM ® -based 32-bit MCUs
+ * Based on reference manuals:
+ *   RM0008 Reference Manual: STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx
+ *   and STM32F107xx advanced ARM-based 32-bit MCUs
+ * and
+ *   RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
+ *   advanced ARM-based 32-bit MCUs
  *
  * Chapter 10.2: External interrupt/event controller (EXTI)
  *
@@ -54,6 +57,8 @@ struct __exti_cb {
 
 #ifdef CONFIG_SOC_SERIES_STM32F1X
 #define EXTI_LINES 19
+#elif CONFIG_SOC_SERIES_STM32F4X
+#define EXTI_LINES 23
 #endif
 
 /* driver data */
@@ -70,7 +75,7 @@ static inline struct stm32_exti *get_exti_base_addr(int line)
 void stm32_exti_enable(int line)
 {
 	volatile struct stm32_exti *exti = get_exti_base_addr(line);
-	int irqnum;
+	int irqnum = 0;
 
 	exti->imr |= 1 << line;
 
@@ -83,6 +88,35 @@ void stm32_exti_enable(int line)
 		/* pins 0..4 are mapped to EXTI0.. EXTI4 */
 		irqnum = STM32F1_IRQ_EXTI0 + line;
 	}
+#elif CONFIG_SOC_SERIES_STM32F4X
+	if (line >= 5 && line <= 9) {
+		irqnum = STM32F4_IRQ_EXTI9_5;
+	} else if (line >= 10 && line <= 15) {
+		irqnum = STM32F4_IRQ_EXTI15_10;
+	} else if (line >= 0 && line <= 4) {
+		/* pins 0..4 are mapped to EXTI0.. EXTI4 */
+		irqnum = STM32F4_IRQ_EXTI0 + line;
+	} else {
+		switch (line) {
+		case 16:
+			irqnum = STM32F4_IRQ_EXTI16;
+			break;
+		case 17:
+			irqnum = STM32F4_IRQ_EXTI17;
+			break;
+		case 18:
+			irqnum = STM32F4_IRQ_EXTI18;
+			break;
+		case 21:
+			irqnum = STM32F4_IRQ_EXTI21;
+			break;
+		case 22:
+			irqnum = STM32F4_IRQ_EXTI22;
+			break;
+		}
+	}
+#else
+	#error "Unknown STM32 SoC"
 #endif
 
 	irq_enable(irqnum);
@@ -199,6 +233,33 @@ static inline void __stm32_exti_isr_15_10(void *arg)
 	__stm32_exti_isr(10, 16, arg);
 }
 
+#ifdef CONFIG_SOC_SERIES_STM32F4X
+static inline void __stm32_exti_isr_16(void *arg)
+{
+	__stm32_exti_isr(16, 17, arg);
+}
+
+static inline void __stm32_exti_isr_17(void *arg)
+{
+	__stm32_exti_isr(17, 18, arg);
+}
+
+static inline void __stm32_exti_isr_18(void *arg)
+{
+	__stm32_exti_isr(18, 19, arg);
+}
+
+static inline void __stm32_exti_isr_21(void *arg)
+{
+	__stm32_exti_isr(21, 22, arg);
+}
+
+static inline void __stm32_exti_isr_22(void *arg)
+{
+	__stm32_exti_isr(22, 23, arg);
+}
+#endif /* CONFIG_SOC_SERIES_STM32F4X */
+
 static void __stm32_exti_connect_irqs(struct device *dev);
 
 /**
@@ -274,7 +335,56 @@ static void __stm32_exti_connect_irqs(struct device *dev)
 		CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI,
 		__stm32_exti_isr_15_10, DEVICE_GET(exti_stm32),
 		0);
-#endif
+#elif CONFIG_SOC_SERIES_STM32F4X
+	IRQ_CONNECT(STM32F4_IRQ_EXTI0,
+		CONFIG_EXTI_STM32_EXTI0_IRQ_PRI,
+		__stm32_exti_isr_0, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI1,
+		CONFIG_EXTI_STM32_EXTI1_IRQ_PRI,
+		__stm32_exti_isr_1, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI2,
+		CONFIG_EXTI_STM32_EXTI2_IRQ_PRI,
+		__stm32_exti_isr_2, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI3,
+		CONFIG_EXTI_STM32_EXTI3_IRQ_PRI,
+		__stm32_exti_isr_3, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI4,
+		CONFIG_EXTI_STM32_EXTI4_IRQ_PRI,
+		__stm32_exti_isr_4, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI9_5,
+		CONFIG_EXTI_STM32_EXTI9_5_IRQ_PRI,
+		__stm32_exti_isr_9_5, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI15_10,
+		CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI,
+		__stm32_exti_isr_15_10, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI16,
+		CONFIG_EXTI_STM32_EXTI16_IRQ_PRI,
+		__stm32_exti_isr_16, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI17,
+		CONFIG_EXTI_STM32_EXTI17_IRQ_PRI,
+		__stm32_exti_isr_17, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI18,
+		CONFIG_EXTI_STM32_EXTI18_IRQ_PRI,
+		__stm32_exti_isr_18, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI21,
+		CONFIG_EXTI_STM32_EXTI21_IRQ_PRI,
+		__stm32_exti_isr_21, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(STM32F4_IRQ_EXTI22,
+		CONFIG_EXTI_STM32_EXTI22_IRQ_PRI,
+		__stm32_exti_isr_22, DEVICE_GET(exti_stm32),
+		0);
+#endif /* CONFIG_SOC_SERIES_STM32FXX */
 }
 
 
diff --git a/drivers/interrupt_controller/exti_stm32.h b/drivers/interrupt_controller/exti_stm32.h
index ad753d6c4e6..ff33fafdeea 100644
--- a/drivers/interrupt_controller/exti_stm32.h
+++ b/drivers/interrupt_controller/exti_stm32.h
@@ -17,11 +17,14 @@
 /**
  * @brief Driver for External interrupt/event controller in STM32 MCUs
  *
- * Based on reference manual:
- *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
- *   advanced ARM ® -based 32-bit MCUs
+ * Based on reference manuals:
+ *   RM0008 Reference Manual: STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx
+ *   and STM32F107xx advanced ARM-based 32-bit MCUs
+ * and
+ *   RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
+ *   advanced ARM-based 32-bit MCUs
  *
- * Chapter 8.2: External interrupt/event controller (EXTI)
+ * Chapter 10.2: External interrupt/event controller (EXTI)
  *
  */