From 95e4b3eb2c2a7e1904f51a3ece16abdd1c8acd97 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 13 Feb 2021 15:07:37 -0600 Subject: [PATCH] arch: arm: Add initial support for Cortex-M55 Core MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for the Cortex-M55 Core which is an implementation of the Armv8.1-M mainline architecture and includes support for the M‑profile Vector Extension (MVE). The support is based on the Cortex-M33 support that already exists in Zephyr. Signed-off-by: Kumar Gala --- CODEOWNERS | 1 + arch/arm/core/aarch32/cortex_m/Kconfig | 19 ++++++++++++ arch/arm/core/aarch32/cortex_m/mpu/arm_mpu.c | 3 +- cmake/gcc-m-cpu.cmake | 6 ++++ drivers/timer/Kconfig | 4 ++- dts/arm/armv8.1-m.dtsi | 29 +++++++++++++++++++ .../interrupt-controller/arm,v8.1m-nvic.yaml | 21 ++++++++++++++ dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml | 14 +++++++++ include/arch/arm/aarch32/cortex_m/cmsis.h | 4 +++ .../arch/arm/aarch32/cortex_m/memory_map.h | 6 ++-- .../arch/arm/aarch32/cortex_m/mpu/arm_mpu.h | 3 +- include/arch/arm/aarch32/cortex_m/nvic.h | 10 ++++--- 12 files changed, 111 insertions(+), 9 deletions(-) create mode 100644 dts/arm/armv8.1-m.dtsi create mode 100644 dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml create mode 100644 dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml diff --git a/CODEOWNERS b/CODEOWNERS index f2bd22681fb..a2ae718d4da 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -350,6 +350,7 @@ /dts/riscv/microsemi-miv.dtsi @galak /dts/riscv/rv32m1* @MaureenHelm /dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda +/dts/arm/armv*m.dtsi @galak @ioannisg /dts/arm/armv7-r.dtsi @bbolen @stephanosio /dts/arm/armv8-a.dtsi @carlocaione /dts/arm/xilinx/ @bbolen @stephanosio diff --git a/arch/arm/core/aarch32/cortex_m/Kconfig b/arch/arm/core/aarch32/cortex_m/Kconfig index 4c255ed9ea7..e8c6db4a884 100644 --- a/arch/arm/core/aarch32/cortex_m/Kconfig +++ b/arch/arm/core/aarch32/cortex_m/Kconfig @@ -62,6 +62,15 @@ config CPU_CORTEX_M33 help This option signifies the use of a Cortex-M33 CPU +config CPU_CORTEX_M55 + bool + select CPU_CORTEX_M + select ARMV8_1_M_MAINLINE + select ARMV8_M_SE if CPU_HAS_TEE + select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU + help + This option signifies the use of a Cortex-M55 CPU + config CPU_CORTEX_M7 bool select CPU_CORTEX_M @@ -213,6 +222,16 @@ config ARMV8_M_MAINLINE ARMv8-M Main Extension includes additional features not present in the ARMv7-M architecture. +config ARMV8_1_M_MAINLINE + bool + select ARMV8_M_MAINLINE + help + This option signifies the use of an ARMv8.1-M processor + implementation, supporting the Main Extension. + + ARMv8.1-M Main Extension includes additional features + not present in the ARMv8-M architecture. + config ARMV8_M_SE bool depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE diff --git a/arch/arm/core/aarch32/cortex_m/mpu/arm_mpu.c b/arch/arm/core/aarch32/cortex_m/mpu/arm_mpu.c index c892c2f288a..bc0874a3ede 100644 --- a/arch/arm/core/aarch32/cortex_m/mpu/arm_mpu.c +++ b/arch/arm/core/aarch32/cortex_m/mpu/arm_mpu.c @@ -71,7 +71,8 @@ static inline uint8_t get_num_regions(void) defined(CONFIG_CPU_CORTEX_M7) #include "arm_mpu_v7_internal.h" #elif defined(CONFIG_CPU_CORTEX_M23) || \ - defined(CONFIG_CPU_CORTEX_M33) + defined(CONFIG_CPU_CORTEX_M33) || \ + defined(CONFIG_CPU_CORTEX_M55) #include "arm_mpu_v8_internal.h" #else #error "Unsupported ARM CPU" diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake index 236ce6998cf..f5ef7f01911 100644 --- a/cmake/gcc-m-cpu.cmake +++ b/cmake/gcc-m-cpu.cmake @@ -24,6 +24,12 @@ if("${ARCH}" STREQUAL "arm") else() set(GCC_M_CPU cortex-m33+nodsp) endif() + elseif(CONFIG_CPU_CORTEX_M55) + if (CONFIG_ARMV8_M_DSP) + set(GCC_M_CPU cortex-m55) + else() + set(GCC_M_CPU cortex-m55+nodsp) + endif() elseif(CONFIG_CPU_CORTEX_R4) set(GCC_M_CPU cortex-r4) elseif(CONFIG_CPU_CORTEX_R5) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index b17dff0d1ab..5ab5e6ce7a8 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -92,13 +92,15 @@ config ARM_ARCH_TIMER DT_COMPAT_ARM_V6M_SYSTICK := arm,armv6m-systick DT_COMPAT_ARM_V7M_SYSTICK := arm,armv7m-systick DT_COMPAT_ARM_V8M_SYSTICK := arm,armv8m-systick +DT_COMPAT_ARM_V8_1M_SYSTICK := arm,armv8.1m-systick config CORTEX_M_SYSTICK bool "Cortex-M SYSTICK timer" depends on CPU_CORTEX_M_HAS_SYSTICK default $(dt_compat_enabled,$(DT_COMPAT_ARM_V6M_SYSTICK)) || \ $(dt_compat_enabled,$(DT_COMPAT_ARM_V7M_SYSTICK)) || \ - $(dt_compat_enabled,$(DT_COMPAT_ARM_V8M_SYSTICK)) + $(dt_compat_enabled,$(DT_COMPAT_ARM_V8M_SYSTICK)) || \ + $(dt_compat_enabled,$(DT_COMPAT_ARM_V8_1M_SYSTICK)) select TICKLESS_CAPABLE help This module implements a kernel device driver for the Cortex-M processor diff --git a/dts/arm/armv8.1-m.dtsi b/dts/arm/armv8.1-m.dtsi new file mode 100644 index 00000000000..5f318f5fec7 --- /dev/null +++ b/dts/arm/armv8.1-m.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" + +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&nvic>; + ranges; + + nvic: interrupt-controller@e000e100 { + compatible = "arm,v8.1m-nvic"; + reg = <0xe000e100 0xc00>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + systick: timer@e000e010 { + compatible = "arm,armv8.1m-systick"; + reg = <0xe000e010 0x10>; + }; + }; +}; diff --git a/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml new file mode 100644 index 00000000000..cb1e26e7429 --- /dev/null +++ b/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml @@ -0,0 +1,21 @@ +description: ARMv8.1-M NVIC (Nested Vectored Interrupt Controller) + +compatible: "arm,v8.1m-nvic" + +include: [interrupt-controller.yaml, base.yaml] + +properties: + reg: + required: true + + arm,num-irq-priority-bits: + required: true + type: int + description: number of bits of IRQ priorities + + "#interrupt-cells": + const: 2 + +interrupt-cells: + - irq + - priority diff --git a/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml new file mode 100644 index 00000000000..610ec29daa6 --- /dev/null +++ b/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml @@ -0,0 +1,14 @@ +description: ARMv8.1-M MPU (Memory Protection Unit) + +compatible: "arm,armv8.1m-mpu" + +include: base.yaml + +properties: + reg: + required: true + + arm,num-mpu-regions: + required: true + type: int + description: number of MPU regions supported by hardware diff --git a/include/arch/arm/aarch32/cortex_m/cmsis.h b/include/arch/arm/aarch32/cortex_m/cmsis.h index 4c5a412ddab..f562c61774d 100644 --- a/include/arch/arm/aarch32/cortex_m/cmsis.h +++ b/include/arch/arm/aarch32/cortex_m/cmsis.h @@ -82,6 +82,8 @@ typedef enum { #define __CM23_REV 0 #elif defined(CONFIG_CPU_CORTEX_M33) #define __CM33_REV 0 +#elif defined(CONFIG_CPU_CORTEX_M55) +#define __CM55_REV 0 #else #error "Unknown Cortex-M device" #endif @@ -117,6 +119,8 @@ typedef enum { #include #elif defined(CONFIG_CPU_CORTEX_M33) #include +#elif defined(CONFIG_CPU_CORTEX_M55) +#include #else #error "Unknown Cortex-M device" #endif diff --git a/include/arch/arm/aarch32/cortex_m/memory_map.h b/include/arch/arm/aarch32/cortex_m/memory_map.h index 655246abc96..86e131e7027 100644 --- a/include/arch/arm/aarch32/cortex_m/memory_map.h +++ b/include/arch/arm/aarch32/cortex_m/memory_map.h @@ -65,7 +65,9 @@ #define _PPB_INT_RSVD_1 0xE0003000 #define _PPB_INT_SCS 0xE000E000 #define _PPB_INT_RSVD_2 0xE000F000 -#elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) +#elif defined(CONFIG_CPU_CORTEX_M23) || \ + defined(CONFIG_CPU_CORTEX_M33) || \ + defined(CONFIG_CPU_CORTEX_M55) #define _PPB_INT_RSVD_0 0xE0000000 #define _PPB_INT_SCS 0xE000E000 #define _PPB_INT_SCB 0xE000ED00 @@ -86,7 +88,7 @@ #define _PPB_EXT_PPB 0xE0042000 #define _PPB_EXT_ROM_TABLE 0xE00FF000 #define _PPB_EXT_END_ADDR 0xE00FFFFF -#elif defined(CONFIG_CPU_CORTEX_M33) +#elif defined(CONFIG_CPU_CORTEX_M33) || defined(CONFIG_CPU_CORTEX_M55) #undef _PPB_EXT_BASE_ADDR #define _PPB_EXT_BASE_ADDR 0xE0044000 #define _PPB_EXT_ROM_TABLE 0xE00FF000 diff --git a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h index 1ddb52bf08e..1f17fe090ff 100644 --- a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h +++ b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h @@ -12,7 +12,8 @@ defined(CONFIG_CPU_CORTEX_M7) #include #elif defined(CONFIG_CPU_CORTEX_M23) || \ - defined(CONFIG_CPU_CORTEX_M33) + defined(CONFIG_CPU_CORTEX_M33) || \ + defined(CONFIG_CPU_CORTEX_M55) #include #else #error "Unsupported ARM CPU" diff --git a/include/arch/arm/aarch32/cortex_m/nvic.h b/include/arch/arm/aarch32/cortex_m/nvic.h index 9bb8bee7856..fa197c39280 100644 --- a/include/arch/arm/aarch32/cortex_m/nvic.h +++ b/include/arch/arm/aarch32/cortex_m/nvic.h @@ -7,11 +7,13 @@ #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_ #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_ -#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) -/* The order here is on purpose since ARMv8-M SoCs may define - * CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE - * so we want to check for ARMv8-M first. +#if defined(CONFIG_ARMV8_1_M_MAINLINE) +/* The order here is on purpose since ARMv8.1-M SoCs may define + * CONFIG_ARMV6_M_ARMV8_M_BASELINE, CONFIG_ARMV7_M_ARMV8_M_MAINLINE or + * CONFIG_ARMV8_M_MAINLINE so we want to check for ARMv8.1-M first. */ +#define NVIC_NODEID DT_INST(0, arm_v8_1m_nvic) +#elif defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) #define NVIC_NODEID DT_INST(0, arm_v8m_nvic) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #define NVIC_NODEID DT_INST(0, arm_v7m_nvic)