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arch: arm: Fix 14.4 guideline violation

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The controlling expression of an if statement has to be an
essentially boolean type.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit is contained in:
Flavio Ceolin 2021-04-02 16:42:16 -07:00 • committed by Anas Nashif
commit 95cd021cea
7 changed files with 10 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c
View file

@ -45,7 +45,7 @@ static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size,
{ {
int flags = 0; int flags = 0;
if (force_npriv) { if (force_npriv != 0) {
flags |= CMSE_MPU_UNPRIV; flags |= CMSE_MPU_UNPRIV;
} }
if (rw) { if (rw) {
@ -141,7 +141,7 @@ static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t s
{ {
int flags = CMSE_NONSECURE; int flags = CMSE_NONSECURE;
if (force_npriv) { if (force_npriv != 0) {
flags |= CMSE_MPU_UNPRIV; flags |= CMSE_MPU_UNPRIV;
} }
if (rw) { if (rw) {

4
arch/arm/core/aarch32/cortex_m/fault.c
View file

@ -243,7 +243,7 @@ static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) { if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
mmfar = temp; mmfar = temp;
PR_EXC(" MMFAR Address: 0x%x", mmfar); PR_EXC(" MMFAR Address: 0x%x", mmfar);
if (from_hard_fault) { if (from_hard_fault != 0) {
/* clear SCB_MMAR[VALID] to reset */ /* clear SCB_MMAR[VALID] to reset */
SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk; SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
} }
@ -381,7 +381,7 @@ static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) { if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
PR_EXC(" BFAR Address: 0x%x", bfar); PR_EXC(" BFAR Address: 0x%x", bfar);
if (from_hard_fault) { if (from_hard_fault != 0) {
/* clear SCB_CFSR_BFAR[VALID] to reset */ /* clear SCB_CFSR_BFAR[VALID] to reset */
SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk; SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
} }

2
arch/arm/core/aarch32/cortex_m/mpu/arm_mpu_v7_internal.h
View file

@ -242,7 +242,7 @@ static inline int is_user_accessible_region(uint32_t r_index, int write)
uint32_t r_ap = get_region_ap(r_index); uint32_t r_ap = get_region_ap(r_index);
if (write) { if (write != 0) {
return r_ap == P_RW_U_RW; return r_ap == P_RW_U_RW;
} }

2
arch/arm/core/aarch32/cortex_m/mpu/nxp_mpu.c
View file

@ -526,7 +526,7 @@ static inline int is_user_accessible_region(uint32_t r_index, int write)
{ {
uint32_t r_ap = SYSMPU->WORD[r_index][2]; uint32_t r_ap = SYSMPU->WORD[r_index][2];
if (write) { if (write != 0) {
return (r_ap & MPU_REGION_WRITE) == MPU_REGION_WRITE; return (r_ap & MPU_REGION_WRITE) == MPU_REGION_WRITE;
} }

2
arch/arm/core/aarch32/thread.c
View file

@ -358,7 +358,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
#if defined(CONFIG_MULTITHREADING) #if defined(CONFIG_MULTITHREADING)
const struct k_thread *thread = _current; const struct k_thread *thread = _current;
if (!thread) { if (thread == NULL) {
return 0; return 0;
} }
#endif #endif

4
include/arch/arm/aarch32/asm_inline_gcc.h
View file

@ -84,7 +84,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key) static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{ {
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
if (key) { if (key != 0U) {
return; return;
} }
__asm__ volatile( __asm__ volatile(
@ -97,7 +97,7 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
"isb;" "isb;"
: : "r"(key) : "memory"); : : "r"(key) : "memory");
#elif defined(CONFIG_ARMV7_R) #elif defined(CONFIG_ARMV7_R)
if (key) { if (key != 0U) {
return; return;
} }
__asm__ volatile( __asm__ volatile(

2
include/arch/arm/aarch32/irq.h
View file

@ -147,7 +147,7 @@ static inline void arch_isr_direct_footer(int maybe_swap)
#ifdef CONFIG_TRACING #ifdef CONFIG_TRACING
sys_trace_isr_exit(); sys_trace_isr_exit();
#endif #endif
if (maybe_swap) { if (maybe_swap != 0) {
z_arm_int_exit(); z_arm_int_exit();
} }
} }