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riscv: abstract RV32E register access

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... and avoid macro duplication.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-06-15 18:41:36 -04:00 • committed by Anas Nashif
commit 95b18c7f9f
3 changed files with 40 additions and 52 deletions
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9
arch/riscv/core/asm_macros.inc
View file

@ -76,3 +76,12 @@
.endr
999:
.endm
/* lowest common denominator for register availability */
#if defined(CONFIG_RISCV_ISA_RV32E)
#define RV_E(op...) op
#define RV_I(op...) /* unavailable */
#else
#define RV_E(op...) op
#define RV_I(op...) op
#endif

47
arch/riscv/core/isr.S
View file

@ -42,38 +42,25 @@
op fa7, __z_arch_esf_t_fa7_OFFSET(reg) ;
#define DO_CALLER_SAVED_T0T1(op) \
op t0, __z_arch_esf_t_t0_OFFSET(sp) ;\
op t1, __z_arch_esf_t_t1_OFFSET(sp)
RV_E( op t0, __z_arch_esf_t_t0_OFFSET(sp) );\
RV_E( op t1, __z_arch_esf_t_t1_OFFSET(sp) )
#if defined(CONFIG_RISCV_ISA_RV32E)
#define DO_CALLER_SAVED_REST(op) \
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\
op a0, __z_arch_esf_t_a0_OFFSET(sp) ;\
op a1, __z_arch_esf_t_a1_OFFSET(sp) ;\
op a2, __z_arch_esf_t_a2_OFFSET(sp) ;\
op a3, __z_arch_esf_t_a3_OFFSET(sp) ;\
op a4, __z_arch_esf_t_a4_OFFSET(sp) ;\
op a5, __z_arch_esf_t_a5_OFFSET(sp) ;\
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
op ra, __z_arch_esf_t_ra_OFFSET(sp)
#else
#define DO_CALLER_SAVED_REST(op) \
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\
op t3, __z_arch_esf_t_t3_OFFSET(sp) ;\
op t4, __z_arch_esf_t_t4_OFFSET(sp) ;\
op t5, __z_arch_esf_t_t5_OFFSET(sp) ;\
op t6, __z_arch_esf_t_t6_OFFSET(sp) ;\
op a0, __z_arch_esf_t_a0_OFFSET(sp) ;\
op a1, __z_arch_esf_t_a1_OFFSET(sp) ;\
op a2, __z_arch_esf_t_a2_OFFSET(sp) ;\
op a3, __z_arch_esf_t_a3_OFFSET(sp) ;\
op a4, __z_arch_esf_t_a4_OFFSET(sp) ;\
op a5, __z_arch_esf_t_a5_OFFSET(sp) ;\
op a6, __z_arch_esf_t_a6_OFFSET(sp) ;\
op a7, __z_arch_esf_t_a7_OFFSET(sp) ;\
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
op ra, __z_arch_esf_t_ra_OFFSET(sp)
#endif /* CONFIG_RISCV_ISA_RV32E */
RV_E( op t2, __z_arch_esf_t_t2_OFFSET(sp) );\
RV_I( op t3, __z_arch_esf_t_t3_OFFSET(sp) );\
RV_I( op t4, __z_arch_esf_t_t4_OFFSET(sp) );\
RV_I( op t5, __z_arch_esf_t_t5_OFFSET(sp) );\
RV_I( op t6, __z_arch_esf_t_t6_OFFSET(sp) );\
RV_E( op a0, __z_arch_esf_t_a0_OFFSET(sp) );\
RV_E( op a1, __z_arch_esf_t_a1_OFFSET(sp) );\
RV_E( op a2, __z_arch_esf_t_a2_OFFSET(sp) );\
RV_E( op a3, __z_arch_esf_t_a3_OFFSET(sp) );\
RV_E( op a4, __z_arch_esf_t_a4_OFFSET(sp) );\
RV_E( op a5, __z_arch_esf_t_a5_OFFSET(sp) );\
RV_I( op a6, __z_arch_esf_t_a6_OFFSET(sp) );\
RV_I( op a7, __z_arch_esf_t_a7_OFFSET(sp) );\
RV_E( op tp, __z_arch_esf_t_tp_OFFSET(sp) );\
RV_E( op ra, __z_arch_esf_t_ra_OFFSET(sp) )
#ifdef CONFIG_SMP
#define GET_CURRENT_CPU(dst, tmp) \

36
arch/riscv/core/switch.S
View file

@ -14,29 +14,21 @@
/* Convenience macros for loading/storing register states. */
#if defined(CONFIG_RISCV_ISA_RV32E)
#define DO_CALLEE_SAVED(op, reg) \
op ra, _thread_offset_to_ra(reg) ;\
op tp, _thread_offset_to_tp(reg) ;\
op s0, _thread_offset_to_s0(reg) ;\
op s1, _thread_offset_to_s1(reg)
#else
#define DO_CALLEE_SAVED(op, reg) \
op ra, _thread_offset_to_ra(reg) ;\
op tp, _thread_offset_to_tp(reg) ;\
op s0, _thread_offset_to_s0(reg) ;\
op s1, _thread_offset_to_s1(reg) ;\
op s2, _thread_offset_to_s2(reg) ;\
op s3, _thread_offset_to_s3(reg) ;\
op s4, _thread_offset_to_s4(reg) ;\
op s5, _thread_offset_to_s5(reg) ;\
op s6, _thread_offset_to_s6(reg) ;\
op s7, _thread_offset_to_s7(reg) ;\
op s8, _thread_offset_to_s8(reg) ;\
op s9, _thread_offset_to_s9(reg) ;\
op s10, _thread_offset_to_s10(reg) ;\
op s11, _thread_offset_to_s11(reg)
#endif /* CONFIG_RISCV_ISA_RV32E */
RV_E( op ra, _thread_offset_to_ra(reg) );\
RV_E( op tp, _thread_offset_to_tp(reg) );\
RV_E( op s0, _thread_offset_to_s0(reg) );\
RV_E( op s1, _thread_offset_to_s1(reg) );\
RV_I( op s2, _thread_offset_to_s2(reg) );\
RV_I( op s3, _thread_offset_to_s3(reg) );\
RV_I( op s4, _thread_offset_to_s4(reg) );\
RV_I( op s5, _thread_offset_to_s5(reg) );\
RV_I( op s6, _thread_offset_to_s6(reg) );\
RV_I( op s7, _thread_offset_to_s7(reg) );\
RV_I( op s8, _thread_offset_to_s8(reg) );\
RV_I( op s9, _thread_offset_to_s9(reg) );\
RV_I( op s10, _thread_offset_to_s10(reg) );\
RV_I( op s11, _thread_offset_to_s11(reg) )
#define DO_FP_CALLEE_SAVED(op, reg) \
op fs0, _thread_offset_to_fs0(reg) ;\