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arm: cmsis: Convert _ClearFaults to use direct CMSIS register access

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The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.

Jira: ZEP-1568

Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Kumar Gala 2017-01-25 09:33:03 -06:00 • committed by Maureen Helm
commit 94db819626
2 changed files with 5 additions and 46 deletions
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9
arch/arm/include/cortex_m/exc.h
View file

@ -103,11 +103,12 @@ static ALWAYS_INLINE void _ClearFaults(void)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/* Reset all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
SCB_CFSR_MEMFAULTSR_Msk |
SCB_CFSR_BUSFAULTSR_Msk;
_ScbHardFaultAllFaultsReset();
/* Clear all Hard Faults - HFSR is write-one-to-clear */
SCB->HFSR = 0xffffffff;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */

42
include/arch/arm/cortex_m/scb.h
View file

@ -46,20 +46,6 @@ extern "C" {
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Clear all hard faults (HFSR register)
*
* HFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbHardFaultAllFaultsReset(void)
{
return __scs.scb.hfsr.val = 0xffff;
}
/**
*
* @brief Invalid the value in MMFAR
@ -75,20 +61,6 @@ static inline void _ScbMemFaultMmfarReset(void)
__scs.scb.cfsr.byte.mmfsr.bit.mmarvalid = 0;
}
/**
*
* @brief Clear all MPU faults (MMFSR register)
*
* CFSR/MMFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return 1 if so, 0 otherwise
*/
static inline void _ScbMemFaultAllFaultsReset(void)
{
__scs.scb.cfsr.byte.mmfsr.val = 0xfe;
}
/**
*
* @brief Invalid the value in BFAR
@ -104,20 +76,6 @@ static inline void _ScbBusFaultBfarReset(void)
__scs.scb.cfsr.byte.bfsr.bit.bfarvalid = 0;
}
/**
*
* @brief Clear all bus faults (BFSR register)
*
* CFSR/BFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return N/A
*/
static inline void _ScbBusFaultAllFaultsReset(void)
{
__scs.scb.cfsr.byte.bfsr.val = 0xfe;
}
/**
*
* @brief Clear all usage faults (UFSR register)