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arch/arm: adds initial support for Atmel SAM3X8E processor

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This adds initial support for Atmel SAM3X8E processor, which is
based on ARM Cortex-M3. The SAM3X8E is being used on Arduino Due.

Change-Id: I199efcf29629f9ebacad474e5edc91bc3757f613
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2016-01-20 21:10:59 -08:00 • committed by Anas Nashif
commit 945ebd74be
10 changed files with 901 additions and 0 deletions
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3
arch/arm/soc/atmel_sam3/Kbuild Normal file
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obj-y += soc.o nmi_on_reset.o
obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o

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arch/arm/soc/atmel_sam3/Kconfig Normal file
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# Kconfig - Atmel SAM3 family processor configuration options
#
# Copyright (c) 2016 Intel Corporation.
# Copyright (c) 2014-2015 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
config SOC_ATMEL_SAM3
bool
default n
if SOC_ATMEL_SAM3
config SOC
default atmel_sam3
config NUM_IRQ_PRIO_BITS
int
default 3
#
# SAM3X8E has total 45 peripherals capable of
# generating interrupts.
#
config NUM_IRQS
int
default 45
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 84000000
#
# SRAM address depends on the processor.
#
# SAM3X8E has two SRAM banks:
# 64K @ 0x20000000
# 32K @ 0x20080000
# The first 64K is mirrored at 0x20070000
# to provide one continuous 96K block.
#
config SRAM_SIZE
default 96 if SOC_ATMEL_SAM3X8E
config SRAM_BASE_ADDRESS
default 0x20000000
default 0x20070000 if SOC_ATMEL_SAM3X8E
#
# Atmel SAM3 family has flash starting @ 0x00080000.
#
# SAM3X8E has 512K of flash.
#
config FLASH_SIZE
default 512 if SOC_ATMEL_SAM3X8E
config FLASH_BASE_ADDRESS
default 0x00080000
config SOC_ATMEL_SAM3_EXT_SLCK
bool "Atmel SAM3 to use external crystal oscillator for slow clock"
default n
help
Says y if you want to use external 32 kHz crystal
oscillator to drive the slow clock. Note that this
adds a few seconds to boot time, as the crystal
needs to stabilize after power-up.
Says n if you do not need accraute and precise timers.
The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz.
config SOC_ATMEL_SAM3_EXT_MAINCK
bool "Atmel SAM3 to use external crystal oscillator for main clock"
default n
help
The main clock is being used to drive the PLL, and
thus driving the processor clock.
Says y if you want to use external crystal oscillator
to drive the main clock. Note that this adds about
a second to boot time, as the crystal needs to
stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator
running at 12 MHz.
config SOC_ATMEL_SAM3_PLLA_MULA
hex
default 0x06
help
This is the multiplier (MULA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 6, and DIVA == 1,
PLL is running at 7 times of main clock.
config SOC_ATMEL_SAM3_PLLA_DIVA
hex
default 0x01
help
This is the divider (DIVA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 6, and DIVA == 1,
PLL is running at 7 times of main clock.
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
endif # SOC_ATMEL_SAM3

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arch/arm/soc/atmel_sam3/Kconfig.soc Normal file
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config SOC_ATMEL_SAM3X8E
bool "Atmel SAM3X8E Processor"
select CPU_CORTEX_M
select CPU_CORTEX_M3
select SOC_ATMEL_SAM3

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arch/arm/soc/atmel_sam3/Makefile Normal file
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KBUILD_CFLAGS += $(call cc-option,-mthumb -mcpu=cortex-m3) \
$(call cc-option,-mthumb -march=armv7-m)
KBUILD_AFLAGS += $(KBUILD_CFLAGS)

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arch/arm/soc/atmel_sam3/irq_vector_table.c Normal file
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/*
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief IRQ part of vector table
*
* This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases:
*
* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
* binds _isr_wrapper() to all the IRQ entries in the vector table.
*
* b) When the platform is written so that device ISRs are installed directly in
* the vector table, they are enumerated here.
*/
#include <toolchain.h>
#include <sections.h>
#if defined(CONFIG_CONSOLE_HANDLER)
#include <soc.h>
#include <console/uart_console.h>
#endif /* CONFIG_CONSOLE_HANDLER */
extern void _isr_wrapper(void);
typedef void (*vth)(void); /* Vector Table Handler */
#if defined(CONFIG_SW_ISR_TABLE)
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _isr_wrapper,
};
#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
extern void _irq_spurious(void);
#if defined(CONFIG_CONSOLE_HANDLER)
static void _uart_console_isr(void)
{
uart_console_isr(NULL);
_IntExit();
}
#endif /* CONFIG_CONSOLE_HANDLER */
/* placeholders: fill with real ISRs */
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
#if defined(CONFIG_CONSOLE_HANDLER)
[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
#endif
};
#endif /* CONFIG_SW_ISR_TABLE */

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arch/arm/soc/atmel_sam3/linker.cmd Normal file
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/* linker.cmd - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <arch/arm/cortex_m/scripts/linker.cmd>

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arch/arm/soc/atmel_sam3/nmi_on_reset.S Normal file
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/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Default basic NMI handler before the kernel is up
*
* Provide a default handler for NMI before the system is up. The default action
* is to hard hang, sleeping.
*
* This might be preferable than rebooting to help debugging, or because
* rebooting might trigger the exact same problem over and over.
*/
#define _ASMLANGUAGE
#include <toolchain.h>
#include <sections.h>
_ASM_FILE_PROLOGUE
GTEXT(_SysNmiOnReset)
SECTION_FUNC(TEXT, _SysNmiOnReset)
wfi
b _SysNmiOnReset

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arch/arm/soc/atmel_sam3/soc.c Normal file
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/*
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief System/hardware module for Atmel SAM3 family processor
*
* This module provides routines to initialize and support board-level hardware
* for the Atmel SAM3 family processor.
*/
#include <nanokernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#ifdef CONFIG_RUNTIME_NMI
extern void _NmiInit(void);
#define NMI_INIT() _NmiInit()
#else
#define NMI_INIT()
#endif
/**
* @brief Setup various clock on SoC.
*
* Setup the SoC clocks according to section 28.12 in datasheet.
*
* Assumption:
* SLCK = 32.768kHz
*/
static void clock_init(void)
{
uint32_t tmp;
/* Note:
* Magic numbers below are obtained by reading the registers
* when the SoC was running the SAM-BA bootloader
* (with reserved bits set to 0).
*/
#ifdef CONFIG_SOC_ATMEL_SAM3_EXT_SLCK
/* This part is to switch the slow clock to using
* the external 32 kHz crystal oscillator.
*/
/* Select external crystal */
__SUPC->cr = SUPC_CR_KEY | SUPC_CR_XTALSEL;
/* Wait for oscillator to be stablized */
while (!(__SUPC->sr & SUPC_SR_OSCSEL))
;
#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_SLCK */
#ifdef CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK
/* Start the external main oscillator */
__PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ
| PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN
| PMC_CKGR_MOR_MOSCXTST;
/* Wait for main oscillator to be stablized */
while (!(__PMC->sr & PMC_INT_MOSCXTS))
;
/* Select main oscillator as source since it is more accurate
* according to datasheet.
*/
__PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ
| PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN
| PMC_CKGR_MOR_MOSCXTST | PMC_CKGR_MOR_MOSCSEL;
/* Wait for main oscillator to be selected */
while (!(__PMC->sr & PMC_INT_MOSCSELS))
;
#else
/* Set main fast RC oscillator to 12 MHz */
__PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_12MHZ
| PMC_CKGR_MOR_MOSCRCEN;
/* Wait for main fast RC oscillator to be stablized */
while (!(__PMC->sr & PMC_INT_MOSCRCS))
;
#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK */
/* Use PLLA as master clock.
* According to datasheet, PMC_MCKR must not be programmed in
* a single write operation. So it seems the safe way is to
* get the system to use main clock (by setting CSS). Then set
* the prescaler (PRES). Finally setting it back to using PLL.
*/
/* Switch to main clock first so we can setup PLL */
tmp = __PMC->mckr & ~PMC_MCKR_CSS_MASK;
__PMC->mckr = tmp | PMC_MCKR_CSS_MAIN;
/* Wait for clock selection complete */
while (!(__PMC->sr & PMC_INT_MCKRDY))
;
/* Setup PLLA */
__PMC->ckgr_pllar = PMC_CKGR_PLLAR_DIVA | PMC_CKGR_PLLAR_ONE
| PMC_CKGR_PLLAR_MULA
| PMC_CKGR_PLLAR_PLLACOUNT;
/* Wait for PLL lock */
while (!(__PMC->sr & PMC_INT_LOCKA))
;
/* Setup prescaler */
tmp = __PMC->mckr & ~PMC_MCKR_PRES_MASK;
__PMC->mckr = tmp | PMC_MCKR_PRES_CLK;
/* Wait for main clock setup complete */
while (!(__PMC->sr & PMC_INT_MCKRDY))
;
/* Finally select PLL as clock source */
tmp = __PMC->mckr & ~PMC_MCKR_CSS_MASK;
__PMC->mckr = tmp | PMC_MCKR_CSS_PLLA;
/* Wait for main clock setup complete */
while (!(__PMC->sr & PMC_INT_MCKRDY))
;
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_sam3_init(struct device *arg)
{
uint32_t key;
ARG_UNUSED(arg);
/* Note:
* Magic numbers below are obtained by reading the registers
* when the SoC was running the SAM-BA bootloader
* (with reserved bits set to 0).
*/
key = irq_lock();
/* Setup the vector table offset register (VTOR),
* which is located at the beginning of flash area.
*/
_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
/* Setup the flash controller.
* The bootloader is running @ 48 MHz with
* FWS == 2.
* When running at 84 MHz, FWS == 4 seems
* to be more stable, and allows the board
* to boot.
*/
__EEFC0->fmr = 0x00000400;
__EEFC1->fmr = 0x00000400;
/* Clear all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
_ScbHardFaultAllFaultsReset();
/* Setup master clock */
clock_init();
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
return 0;
}
DECLARE_DEVICE_INIT_CONFIG(atmel_sam3_0, "", atmel_sam3_init, NULL);
SYS_DEFINE_DEVICE(atmel_sam3_0, NULL, PRIMARY, 0);

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/*
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SoC configuration macros for the Atmel SAM3 family processors.
*/
#ifndef _ATMEL_SAM3_SOC_H_
#define _ATMEL_SAM3_SOC_H_
/* IRQ numbers (from section 9.1, Peripheral Identifiers). */
#define IRQ_SUPC 0 /* Supply Controller */
#define IRQ_RSTC 1 /* Reset Controller */
#define IRQ_RTC 2 /* Real-time Clock */
#define IRQ_RTT 3 /* Real-time Timer */
#define IRQ_WDG 4 /* Watchdog Timer */
#define IRQ_PMC 5 /* Power Management Controller */
#define IRQ_EEFC0 6 /* Enhanced Embedded Flash Controller 0 */
#define IRQ_EEFC1 7 /* Enhanced Embedded Flash Controller 1 */
#define IRQ_UART 8 /* UART */
#define IRQ_PIOA 11 /* Parallel IO Controller A */
#define IRQ_PIOB 12 /* Parallel IO Controller B */
#define IRQ_PIOC 13 /* Parallel IO Controller C */
#define IRQ_PIOD 14 /* Parallel IO Controller D */
#define IRQ_PIOE 15 /* Parallel IO Controller E */
#define IRQ_PIOF 16 /* Parallel IO Controller F */
#define IRQ_USART0 17 /* USART #0 */
#define IRQ_USART1 18 /* USART #1 */
#define IRQ_USART2 19 /* USART #2 */
#define IRQ_USART3 20 /* USART #3 */
#define IRQ_HSMCI 21 /* High Speed Multimedia Card Interface */
#define IRQ_TWI0 22 /* Two-wire Interface #0 */
#define IRQ_TWI1 23 /* Two-wire Interface #1 */
#define IRQ_SPI0 24 /* SPI #0 */
#define IRQ_SPI1 25 /* SPI #1 */
#define IRQ_SSC 26 /* Synchronous Serial Controller */
#define IRQ_TC0 27 /* Timer Counter Channel #0 */
#define IRQ_TC1 28 /* Timer Counter Channel #1 */
#define IRQ_TC2 29 /* Timer Counter Channel #2 */
#define IRQ_TC3 30 /* Timer Counter Channel #3 */
#define IRQ_TC4 31 /* Timer Counter Channel #4 */
#define IRQ_TC5 32 /* Timer Counter Channel #5 */
#define IRQ_TC6 33 /* Timer Counter Channel #6 */
#define IRQ_TC7 34 /* Timer Counter Channel #7 */
#define IRQ_TC8 35 /* Timer Counter Channel #8 */
#define IRQ_PWM 36 /* PWM Controller */
#define IRQ_ADC 37 /* ADC Controller */
#define IRQ_DACC 38 /* DAC Controller */
#define IRQ_DMAC 39 /* DMA Controller */
#define IRQ_UOTGHS 40 /* USB OTG High Speed */
#define IRQ_TRNG 41 /* True Random Number Generator */
#define IRQ_EMAC 42 /* Ehternet MAC */
#define IRQ_CAN0 43 /* CAN Controller #0 */
#define IRQ_CAN1 44 /* CAN Controller #1 */
/* PID: Peripheral IDs (from section 9.1, Peripheral Identifiers).
* PMC uses PIDs to enable clock for peripherals.
*/
#define PID_RTC 2 /* Real-time Clock */
#define PID_RTT 3 /* Real-time Timer */
#define PID_WDG 4 /* Watchdog Timer */
#define PID_PMC 5 /* Power Management Controller */
#define PID_EEFC0 6 /* Enhanced Embedded Flash Controller 0 */
#define PID_EEFC1 7 /* Enhanced Embedded Flash Controller 1 */
#define PID_UART 8 /* UART */
#define PID_PIOA 11 /* Parallel IO Controller A */
#define PID_PIOB 12 /* Parallel IO Controller B */
#define PID_PIOC 13 /* Parallel IO Controller C */
#define PID_PIOD 14 /* Parallel IO Controller D */
#define PID_PIOE 15 /* Parallel IO Controller E */
#define PID_PIOF 16 /* Parallel IO Controller F */
#define PID_USART0 17 /* USART #0 */
#define PID_USART1 18 /* USART #1 */
#define PID_USART2 19 /* USART #2 */
#define PID_USART3 20 /* USART #3 */
#define PID_HSMCI 21 /* High Speed Multimedia Card Interface */
#define PID_TWI0 22 /* Two-wire Interface #0 */
#define PID_TWI1 23 /* Two-wire Interface #1 */
#define PID_SPI0 24 /* SPI #0 */
#define PID_SPI1 25 /* SPI #1 */
#define PID_SSC 26 /* Synchronous Serial Controller */
#define PID_TC0 27 /* Timer Counter Channel #0 */
#define PID_TC1 28 /* Timer Counter Channel #1 */
#define PID_TC2 29 /* Timer Counter Channel #2 */
#define PID_TC3 30 /* Timer Counter Channel #3 */
#define PID_TC4 31 /* Timer Counter Channel #4 */
#define PID_TC5 32 /* Timer Counter Channel #5 */
#define PID_TC6 33 /* Timer Counter Channel #6 */
#define PID_TC7 34 /* Timer Counter Channel #7 */
#define PID_TC8 35 /* Timer Counter Channel #8 */
#define PID_PWM 36 /* PWM Controller */
#define PID_ADC 37 /* ADC Controller */
#define PID_DACC 38 /* DAC Controller */
#define PID_DMAC 39 /* DMA Controller */
#define PID_UOTGHS 40 /* USB OTG High Speed */
#define PID_TRNG 41 /* True Random Number Generator */
#define PID_EMAC 42 /* Ehternet MAC */
#define PID_CAN0 43 /* CAN Controller #0 */
#define PID_CAN1 44 /* CAN Controller #1 */
/* Power Manager Controller */
#define PMC_ADDR 0x400E0600
#define PMC_CKGR_UCKR_UPLLEN (1 << 16)
#define PMC_CKGR_UCKR_UPLLCOUNT (3 << 20)
#define PMC_CKGR_MOR_KEY (0x37 << 16)
#define PMC_CKGR_MOR_MOSCXTST (0xFF << 8)
#define PMC_CKGR_MOR_MOSCXTEN (1 << 0)
#define PMC_CKGR_MOR_MOSCRCEN (1 << 3)
#define PMC_CKGR_MOR_MOSCRCF_4MHZ (0 << 4)
#define PMC_CKGR_MOR_MOSCRCF_8MHZ (1 << 4)
#define PMC_CKGR_MOR_MOSCRCF_12MHZ (2 << 4)
#define PMC_CKGR_MOR_MOSCSEL (1 << 24)
#define PMC_CKGR_PLLAR_PLLACOUNT (0x3F << 8)
#define PMC_CKGR_PLLAR_ONE (1 << 29)
/*
* PLL clock = Main * (MULA + 1) / DIVA
*
* By default, MULA == 6, DIVA == 1.
* With main crystal running at 12 MHz,
* PLL = 12 * (6 + 1) / 1 = 84 MHz
*
* With processor clock prescaler at 1,
* the processor clock is at 84 MHz.
*/
#define PMC_CKGR_PLLAR_MULA \
((CONFIG_SOC_ATMEL_SAM3_PLLA_MULA) << 16)
#define PMC_CKGR_PLLAR_DIVA \
((CONFIG_SOC_ATMEL_SAM3_PLLA_DIVA) << 0)
#define PMC_MCKR_CSS_MASK (0x3)
#define PMC_MCKR_CSS_SLOW (0 << 0)
#define PMC_MCKR_CSS_MAIN (1 << 0)
#define PMC_MCKR_CSS_PLLA (2 << 0)
#define PMC_MCKR_CSS_UPLL (3 << 0)
#define PMC_MCKR_PRES_MASK (0x70)
#define PMC_MCKR_PRES_CLK (0 << 4)
#define PMC_MCKR_PRES_DIV2 (1 << 4)
#define PMC_MCKR_PRES_DIV4 (2 << 4)
#define PMC_MCKR_PRES_DIV8 (3 << 4)
#define PMC_MCKR_PRES_DIV16 (4 << 4)
#define PMC_MCKR_PRES_DIV32 (5 << 4)
#define PMC_MCKR_PRES_DIV64 (6 << 4)
#define PMC_MCKR_PRES_DIV3 (7 << 4)
#define PMC_MCKR_PLLADIV2 (1 << 12)
#define PMC_MCKR_UPLLDIV2 (1 << 13)
#define PMC_INT_MOSCXTS (1 << 0)
#define PMC_INT_LOCKA (1 << 1)
#define PMC_INT_MCKRDY (1 << 3)
#define PMC_INT_LOCKU (1 << 6)
#define PMC_INT_OSCSELS (1 << 7)
#define PMC_INT_PCKRDY0 (1 << 8)
#define PMC_INT_PCKRDY1 (1 << 9)
#define PMC_INT_PCKRDY2 (1 << 10)
#define PMC_INT_MOSCSELS (1 << 16)
#define PMC_INT_MOSCRCS (1 << 17)
#define PMC_INT_CFDEV (1 << 18)
#define PMC_INT_CFDS (1 << 19)
#define PMC_INT_FOS (1 << 20)
/* UART */
#define UART_ADDR 0x400E0800
/* EEFC */
#define EEFC_BANK0_ADDR 0x400E0A00
#define EEFC_BANK1_ADDR 0x400E0C00
/* PIO Controllers */
#define PIOA_ADDR 0x400E0E00
#define PIOB_ADDR 0x400E1000
#define PIOC_ADDR 0x400E1200
#define PIOD_ADDR 0x400E1400
#define PIOE_ADDR 0x400E1600
#define PIOF_ADDR 0x400E1800
/* Supply Controller (SUPC) */
#define SUPC_ADDR 0x400E1A10
#define SUPC_CR_KEY (0xA5 << 24)
#define SUPC_CR_XTALSEL (1 << 3)
#define SUPC_SR_OSCSEL (1 << 7)
#ifndef _ASMLANGUAGE
#include <device.h>
#include <misc/util.h>
#include <drivers/rand32.h>
#include "soc_registers.h"
/* uart configuration settings */
#define UART_IRQ_FLAGS 0
/* EEFC Register struct */
#define __EEFC0 ((volatile struct __eefc *)EEFC_BANK0_ADDR)
#define __EEFC1 ((volatile struct __eefc *)EEFC_BANK1_ADDR)
/* PMC Register struct */
#define __PMC ((volatile struct __pmc *)PMC_ADDR)
/* PIO Registers struct */
#define __PIOA ((volatile struct __pio *)PIOA_ADDR)
#define __PIOB ((volatile struct __pio *)PIOB_ADDR)
#define __PIOC ((volatile struct __pio *)PIOC_ADDR)
#define __PIOD ((volatile struct __pio *)PIOD_ADDR)
#define __PIOE ((volatile struct __pio *)PIOE_ADDR)
#define __PIOF ((volatile struct __pio *)PIOF_ADDR)
/* Supply Controller Register struct */
#define __SUPC ((volatile struct __supc *)SUPC_ADDR)
#endif /* !_ASMLANGUAGE */
#endif /* _ATMEL_SAM3_SOC_H_ */

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/*
* Copyright (c) 2016 Intel Corporation.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SoC configuration macros for the Atmel SAM3 family processors.
*
* Refer to the datasheet for more information about these registers.
*/
#ifndef _ATMEL_SAM3_SOC_REGS_H_
#define _ATMEL_SAM3_SOC_REGS_H_
/* Enhanced Embedded Flash Controller */
struct __eefc {
uint32_t fmr; /* 0x00 Flash Mode Register */
uint32_t fcr; /* 0x04 Flash Command Register */
uint32_t fsr; /* 0x08 Flash Status Register */
uint32_t frr; /* 0x0C Flash Result Register */
};
/* PIO Controller */
struct __pio {
uint32_t per; /* 0x00 Enable */
uint32_t pdr; /* 0x04 Disable */
uint32_t psr; /* 0x08 Status */
uint32_t res0; /* 0x0C reserved */
uint32_t oer; /* 0x10 Output Enable */
uint32_t odr; /* 0x14 Output Disable */
uint32_t osr; /* 0x18 Output Status */
uint32_t res1; /* 0x1C reserved */
uint32_t ifer; /* 0x20 Glitch Input Filter Enable */
uint32_t ifdr; /* 0x24 Glitch Input Filter Disable */
uint32_t ifsr; /* 0x28 Glitch Input Fitler Status */
uint32_t res2; /* 0x2C reserved */
uint32_t sodr; /* 0x30 Set Output Data */
uint32_t codr; /* 0x34 Clear Output Data */
uint32_t odsr; /* 0x38 Output Data Status */
uint32_t pdsr; /* 0x3C Pin Data Status */
uint32_t ier; /* 0x40 Interrupt Enable */
uint32_t idr; /* 0x44 Interrupt Disable */
uint32_t imr; /* 0x48 Interrupt Mask */
uint32_t isr; /* 0x4C Interrupt Status */
uint32_t mder; /* 0x50 Multi-driver Enable */
uint32_t mddr; /* 0x54 Multi-driver Disable */
uint32_t mdsr; /* 0x58 Multi-driver Status */
uint32_t res3; /* 0x5C reserved */
uint32_t pudr; /* 0x60 Pull-up Disable */
uint32_t puer; /* 0x64 Pull-up Enable */
uint32_t pusr; /* 0x68 Pad Pull-up Status */
uint32_t res4; /* 0x6C reserved */
uint32_t absr; /* 0x70 Peripheral AB Select */
uint32_t res5[3]; /* 0x74-0x7C reserved */
uint32_t scifsr; /* 0x80 System Clock Glitch Input */
/* Filter Select */
uint32_t difsr; /* 0x84 Debouncing Input Filter */
/* Select */
uint32_t ifdgsr; /* 0x88 Glitch or Debouncing Input */
/* Filter Clock Selection */
/* Status */
uint32_t scdr; /* 0x8C Slow Clock Divider Debounce */
uint32_t res6[4]; /* 0x90-0x9C reserved */
uint32_t ower; /* 0xA0 Output Write Enable */
uint32_t owdr; /* 0xA4 Output Write Disable */
uint32_t owsr; /* 0xA8 Output Write Status */
uint32_t res7; /* 0xAC reserved */
uint32_t aimer; /* 0xB0 Additional Interrupt Modes */
/* Enable */
uint32_t aimdr; /* 0xB4 Additional Interrupt Modes */
/* Disable */
uint32_t aimmr; /* 0xB8 Additional Interrupt Modes */
/* Mask */
uint32_t res8; /* 0xBC reserved */
uint32_t esr; /* 0xC0 Edge Select */
uint32_t lsr; /* 0xC4 Level Select */
uint32_t elsr; /* 0xC8 Edge/Level Status */
uint32_t res9; /* 0xCC reserved */
uint32_t fellsr; /* 0xD0 Falling Edge/Low Level Sel */
uint32_t rehlsr; /* 0xD4 Rising Edge/High Level Sel */
uint32_t frlhsr; /* 0xD8 Fall/Rise - Low/High Status */
uint32_t res10; /* 0xDC reserved */
uint32_t locksr; /* 0xE0 Lock Status */
uint32_t wpmr; /* 0xE4 Write Protect Mode */
uint32_t wpsr; /* 0xE8 Write Protect Status */
};
/* Power Management Controller */
struct __pmc {
uint32_t scer; /* 0x00 System Clock Enable */
uint32_t scdr; /* 0x04 System Clock Disable */
uint32_t scsr; /* 0x08 System Clock Status */
uint32_t res0; /* 0x0C reserved */
uint32_t pcer0; /* 0x10 Peripheral Clock Enable 0 */
uint32_t pcdr0; /* 0x14 Peripheral Clock Disable 0 */
uint32_t pcsr0; /* 0x18 Peripheral Clock Status 0 */
uint32_t ckgr_uckr; /* 0x1C UTMI Clock */
uint32_t ckgr_mor; /* 0x20 Main Oscillator */
uint32_t ckgr_mcfr; /* 0x24 Main Clock Freq. */
uint32_t ckgr_pllar; /* 0x28 PLLA */
uint32_t res1; /* 0x2C reserved */
uint32_t mckr; /* 0x30 Master Clock */
uint32_t res2; /* 0x34 reserved */
uint32_t usb; /* 0x38 USB Clock */
uint32_t res3; /* 0x3C reserved */
uint32_t pck0; /* 0x40 Programmable Clock 0 */
uint32_t pck1; /* 0x44 Programmable Clock 1 */
uint32_t pck2; /* 0x48 Programmable Clock 2 */
uint32_t res4[5]; /* 0x4C-0x5C reserved */
uint32_t ier; /* 0x60 Interrupt Enable */
uint32_t idr; /* 0x64 Interrupt Disable */
uint32_t sr; /* 0x68 Status */
uint32_t imr; /* 0x6C Interrupt Mask */
uint32_t fsmr; /* 0x70 Fast Startup Mode */
uint32_t fspr; /* 0x74 Fast Startup Polarity */
uint32_t focr; /* 0x78 Fault Outpu Clear */
uint32_t res5[26]; /* 0x7C-0xE0 reserved */
uint32_t wpmr; /* 0xE4 Write Protect Mode */
uint32_t wpsr; /* 0xE8 Write Protect Status */
uint32_t res6[5]; /* 0xEC-0xFC reserved */
uint32_t pcer1; /* 0x100 Peripheral Clock Enable 1 */
uint32_t pcdr1; /* 0x104 Peripheral Clock Disable 1 */
uint32_t pcsr1; /* 0x108 Peripheral Clock Status 1 */
uint32_t pcr; /* 0x10C Peripheral Control */
};
/* Supply Controller (SUPC) */
struct __supc {
uint32_t cr; /* 0x00 Control */
uint32_t smmr; /* 0x04 Supply Monitor Mode */
uint32_t mr; /* 0x08 Mode */
uint32_t wumr; /* 0x0C Wake Up Mode */
uint32_t wuir; /* 0x10 Wake Up Inputs */
uint32_t sr; /* 0x14 Status */
};
#endif /* _ATMEL_SAM3_SOC_REGS_H_ */