nios2: basic build, non-functional

Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.

This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.

Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

arch/Kconfig

@@ -32,6 +32,9 @@ config X86
 	bool "x86 architecture"
 	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 
+config NIOS2
+	bool "Nios II Gen 2 architecture"
+
 endchoice
 
 #

arch/nios2/Kbuild

@@ -0,0 +1,6 @@
+subdir-ccflags-y +=-I$(srctree)/include/drivers
+subdir-ccflags-y +=-I$(srctree)/drivers
+subdir-asflags-y += $(subdir-ccflags-y)
+
+obj-y += soc/$(SOC_PATH)/
+obj-y += core/

arch/nios2/Kconfig

@@ -0,0 +1,102 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+	prompt "Nios II configuration selection"
+	depends on NIOS2
+	source "arch/nios2/soc/*/Kconfig.soc"
+endchoice
+
+menu "Nios II Options"
+	depends on NIOS2
+
+config ARCH
+	string
+	default "nios2"
+
+config ARCH_DEFCONFIG
+	string
+	default "arch/nios2/defconfig"
+
+menu "Nios II Gen 2 Processor Options"
+
+config CPU_NIOS2_GEN2
+	bool
+	default y
+	select ATOMIC_OPERATIONS_C
+	help
+	This option signifies the use of a Nios II Gen 2 CPU
+
+endmenu
+
+menu "Nios II Family Options"
+
+# FIXME default is probably bogus
+config RESET_VECTOR
+	prompt "Nios II reset vector"
+	hex
+	default 0x00000000
+
+# FIXME default is probably bogus
+config EXCEPTION_VECTOR
+	prompt "Nios II exception vector"
+	hex
+	default 0x00000004
+
+config XIP
+	bool
+	default y
+
+config SRAM_SIZE
+	int "SRAM Size in kB"
+	help
+	This option specifies the size of the SRAM in kB.  It is normally set
+	by the platform's defconfig file and the user should generally avoid
+	modifying it via the menu configuration.
+
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
+	help
+	This option specifies the base address of the SRAM on the platform.  It
+	is normally set by the platform's defconfig file and the user should
+	generally avoid modifying it via the menu configuration.
+
+config FLASH_SIZE
+	int "Flash Size in kB"
+	help
+	This option specifies the size of the flash in kB.  It is normally set
+	by the platform's defconfig file and the user should generally avoid
+	modifying it via the menu configuration.
+
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the platform.
+	It is normally set by the platform's defconfig file and the user should
+	generally avoid modifying it via the menu configuration.
+
+config IRQ_OFFLOAD
+	bool "Enable IRQ offload"
+	default n
+	help
+	Enable irq_offload() API which allows functions to be synchronously
+	run in interrupt context. Mainly useful for test cases.
+
+endmenu
+
+source "arch/nios2/soc/*/Kconfig"
+
+endmenu

arch/nios2/Makefile

@@ -0,0 +1,2 @@
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
+

arch/nios2/core/Makefile

@@ -0,0 +1,9 @@
+ccflags-y += -I$(srctree)/kernel/nanokernel/include
+ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
+ccflags-y += -I$(srctree)/kernel/microkernel/include
+
+obj-y += reset.o irq_manage.o fatal.o vector_table.o swap.o thread.o \
+	 cpu_idle.o irq_offload.o
+
+obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
+

arch/nios2/core/cpu_idle.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+
+/**
+ *
+ * @brief Power save idle routine
+ *
+ * This function will be called by the nanokernel idle loop or possibly within
+ * an implementation of _sys_power_save_idle in the microkernel when the
+ * '_sys_power_save_flag' variable is non-zero.
+ *
+ * @return N/A
+ */
+void nano_cpu_idle(void)
+{
+	/* STUB */
+}
+
+/**
+ *
+ * @brief Atomically re-enable interrupts and enter low power mode
+ *
+ * This function is utilized by the nanokernel object "wait" APIs for tasks,
+ * e.g. nano_task_lifo_get(), nano_task_sem_take(),
+ * nano_task_stack_pop(), and nano_task_fifo_get().
+ *
+ * INTERNAL
+ * The requirements for nano_cpu_atomic_idle() are as follows:
+ * 1) The enablement of interrupts and entering a low-power mode needs to be
+ *    atomic, i.e. there should be no period of time where interrupts are
+ *    enabled before the processor enters a low-power mode.  See the comments
+ *    in nano_task_lifo_get(), for example, of the race condition that
+ *    occurs if this requirement is not met.
+ *
+ * 2) After waking up from the low-power mode, the interrupt lockout state
+ *    must be restored as indicated in the 'imask' input parameter.
+ *
+ * @return N/A
+ */
+void nano_cpu_atomic_idle(unsigned int key)
+{
+	/* STUB */
+}
+

arch/nios2/core/fatal.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <arch/cpu.h>
+#include <nano_private.h>
+
+const NANO_ESF _default_esf;
+
+FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
+					  const NANO_ESF *esf)
+{
+	ARG_UNUSED(reason);
+	ARG_UNUSED(esf);
+
+	/* STUB */
+	while (1) {
+		/* whee! */
+	}
+}
+

arch/nios2/core/irq_manage.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <arch/cpu.h>
+#include <irq.h>
+
+
+void _arch_irq_enable(unsigned int irq)
+{
+	/* STUB */
+	ARG_UNUSED(irq);
+};
+
+
+void _arch_irq_disable(unsigned int irq)
+{
+	/* STUB */
+	ARG_UNUSED(irq);
+};
+
+
+int _arch_irq_connect_dynamic(unsigned int irq,
+					 unsigned int priority,
+					 void (*routine)(void *parameter),
+					 void *parameter,
+					 uint32_t flags)
+{
+	ARG_UNUSED(irq);
+	ARG_UNUSED(priority);
+	ARG_UNUSED(routine);
+	ARG_UNUSED(parameter);
+	ARG_UNUSED(flags);
+
+	/* STUB. May never implement this, part of a deprecated API */
+	return -1;
+};
+

arch/nios2/core/irq_offload.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+#include <irq_offload.h>
+
+void irq_offload(irq_offload_routine_t routine, void *parameter)
+{
+	/* STUB */
+}
+

arch/nios2/core/offsets/offsets.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Nios II nano kernel structure member offset definition file
+ *
+ * This module is responsible for the generation of the absolute symbols whose
+ * value represents the member offsets for various Nios II nanokernel
+ * structures.
+ *
+ * All of the absolute symbols defined by this module will be present in the
+ * final microkernel or nanokernel ELF image (due to the linker's reference to
+ * the _OffsetAbsSyms symbol).
+ *
+ * INTERNAL
+ * It is NOT necessary to define the offset for every member of a structure.
+ * Typically, only those members that are accessed by assembly language routines
+ * are defined; however, it doesn't hurt to define all fields for the sake of
+ * completeness.
+ */
+
+
+#include <gen_offset.h>
+#include <nano_private.h>
+#include <nano_offsets.h>
+
+/* size of the struct tcs structure sans save area for floating point regs */
+GEN_ABSOLUTE_SYM(__tTCS_NOFLOAT_SIZEOF, sizeof(tTCS));
+
+GEN_ABS_SYM_END

arch/nios2/core/reset.S

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define _ASMLANGUAGE
+
+#include <arch/cpu.h>
+#include <nano_private.h>
+#include <offsets.h>
+
+GTEXT(__start)
+

arch/nios2/core/swap.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+
+unsigned int _Swap(unsigned int eflags)
+{
+	/* STUB ... will probably end up in ASM domain */
+	return 0;
+}

arch/nios2/core/thread.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+
+tNANO _nanokernel = {0};
+
+/**
+ *
+ * @brief Create a new kernel execution context
+ *
+ * This function initializes a thread control structure (TCS) for a
+ * new kernel execution context. A fake stack frame is created as if
+ * the context had been "swapped out" via _Swap()
+ *
+ * @param stack_memory pointer to the context stack area
+ * @param stack_size size of contexts stack area
+ * @param thread_func new contexts entry function
+ * @param parameter1 first entry function parameter
+ * @param parameter2 second entry function parameter
+ * @param parameter3 third entry function parameter
+ * @param priority Priority of the new context
+ * @param options Additional options for the context
+ *
+ * @return none
+ *
+ * \NOMANUAL
+ */
+
+void _new_thread(char *stack_memory, unsigned stack_size,
+		 _thread_entry_t thread_func, void *parameter1,
+		 void *parameter2, void *parameter3, int priority,
+		 unsigned options)
+{
+	/* STUB */
+}

arch/nios2/core/vector_table.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nano_private.h>
+
+void __reset_handler(void)
+{
+	/* stub */
+}
+
+void __exception_handler(void)
+{
+	/* stub */
+}
+
+
+struct vector_table {
+	uint32_t reset;
+	uint32_t exception;
+};
+
+/* FIXME not using CONFIG_RESET_VECTOR or CONFIG_EXCEPTION_VECTOR like we
+ * should
+ */
+struct vector_table _vector_table _GENERIC_SECTION(.exc_vector_table) = {
+	(uint32_t)__reset_handler,
+	(uint32_t)__exception_handler
+};
+
+extern struct vector_table __start _ALIAS_OF(_vector_table);
+

arch/nios2/include/nano_private.h

@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Private nanokernel definitions
+ *
+ * This file contains private nanokernel structures definitions and various
+ * other definitions for the Nios II processor architecture.
+ *
+ * This file is also included by assembly language files which must #define
+ * _ASMLANGUAGE before including this header file.  Note that nanokernel
+ * assembly source files obtains structure offset values via "absolute
+ * symbols" in the offsets.o module.
+ */
+
+#ifndef _NANO_PRIVATE_H
+#define _NANO_PRIVATE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <toolchain.h>
+#include <sections.h>
+#include <arch/cpu.h>
+
+#ifndef _ASMLANGUAGE
+#include <nanokernel.h>            /* public nanokernel API */
+#include <../../../kernel/nanokernel/include/nano_internal.h>
+#include <stdint.h>
+#include <misc/util.h>
+#include <misc/dlist.h>
+#endif
+
+/* Bitmask definitions for the struct tcs->flags bit field */
+#define FIBER          0x000
+#define TASK           0x001 /* 1 = task, 0 = fiber   */
+
+#define INT_ACTIVE     0x002 /* 1 = execution context is interrupt handler */
+#define EXC_ACTIVE     0x004 /* 1 = executino context is exception handler */
+#define USE_FP         0x010 /* 1 = thread uses floating point unit */
+#define PREEMPTIBLE    0x020 /* 1 = preemptible thread */
+#define ESSENTIAL      0x200 /* 1 = system thread that must not abort */
+#define NO_METRICS     0x400 /* 1 = _Swap() not to update task metrics */
+
+/* stacks */
+
+#define STACK_ALIGN_SIZE 4
+
+#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
+#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
+
+#ifndef _ASMLANGUAGE
+
+struct irq_stack_frame {
+	int stub;
+};
+
+typedef struct irq_stack_frame tISF;
+
+struct callee_saved {
+	int stub;
+};
+
+typedef struct callee_saved tCalleeSaved;
+
+struct coop {
+	int stub;
+};
+
+struct preempt {
+	int stub;
+};
+
+struct tcs {
+	struct tcs *link;         /* node in singly-linked list
+				   * _nanokernel.fibers
+				   */
+	uint32_t flags;           /* bitmask of flags above */
+	int prio;                 /* fiber priority, -1 for a task */
+	struct coop coopReg;
+	struct preempt preempReg;
+#ifdef CONFIG_ERRNO
+	int errno_var;
+#endif
+#ifdef CONFIG_NANO_TIMEOUTS
+	struct _nano_timeout nano_timeout;
+#endif
+#if defined(CONFIG_THREAD_MONITOR)
+	struct __thread_entry *entry; /* thread entry and parameters description */
+	struct tcs *next_thread; /* next item in list of ALL fiber+tasks */
+#endif
+};
+
+struct s_NANO {
+	struct tcs *fiber;    /* singly linked list of runnable fibers */
+	struct tcs *task;     /* current task the nanokernel knows about */
+	struct tcs *current;  /* currently scheduled thread (fiber or task) */
+
+#if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
+	sys_dlist_t timeout_q;
+	int32_t task_timeout;
+#endif
+#if defined(CONFIG_THREAD_MONITOR)
+	struct tcs *threads; /* singly linked list of ALL fiber+tasks */
+#endif
+};
+
+typedef struct s_NANO tNANO;
+extern tNANO _nanokernel;
+
+
+/* Arch-specific nanokernel APIs */
+void nano_cpu_idle(void);
+void nano_cpu_atomic_idle(unsigned int key);
+
+static ALWAYS_INLINE void nanoArchInit(void)
+{
+	/* STUB */
+}
+
+static ALWAYS_INLINE void fiberRtnValueSet(struct tcs *fiber,
+					   unsigned int value)
+{
+	ARG_UNUSED(fiber);
+	ARG_UNUSED(value);
+	/* STUB */
+}
+
+static inline void _IntLibInit(void)
+{
+	/* STUB ... possibly nothing to do here though */
+}
+
+FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
+					  const NANO_ESF *esf);
+
+
+static ALWAYS_INLINE int _IS_IN_ISR(void)
+{
+	/* STUB */
+	return 0;
+}
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _NANO_PRIVATE_H */
+

arch/nios2/soc/nios2e-zephyr/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/nios2/include/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/nios2/soc/nios2e-zephyr/Kconfig.defconfig

@@ -0,0 +1,11 @@
+if SOC_NIOS2E_ZEPHYR
+
+config SOC
+	string
+	default nios2e-zephyr
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 1000000
+
+endif

arch/nios2/soc/nios2e-zephyr/Kconfig.soc

@@ -0,0 +1,3 @@
+config SOC_NIOS2E_ZEPHYR
+	bool "Nios IIe - Zephyr Golden Configuration"
+

arch/nios2/soc/nios2e-zephyr/Makefile

@@ -0,0 +1,16 @@
+# FIXME: Gets rid of bizzarre linker errors in the form:
+# "warning: global pointer relative relocation at address 0x100013a8 when _gp
+# not defined"
+# However disabling global pointer  may be a performance issue...
+# May be related to the bogus temporary FLASH and RAM base addresses we are
+# using since they are 256MB apart, or we're possibly discarding a Nios2-
+# specific section that we need to include in the linker script.
+arch_cflags := $(call cc-option,-G0)
+
+# FIXME I got tired of adding ARG_UNUSED to all the stubs, sanitycheck treats
+# warnings as errors. Remove this once the stubs are all implemented
+arch_cflags += $(call cc-option,-Wno-unused-parameter)
+
+KBUILD_AFLAGS += $(arch_cflags)
+KBUILD_CFLAGS += $(arch_cflags)
+KBUILD_CXXFLAGS += $(arch_cflags)

arch/nios2/soc/nios2e-zephyr/linker.cmd

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Nios II/e CPU with timer and 16550 UART
+ */
+
+#include <arch/nios2/linker.cmd>

boards/altera_max10/Kconfig.board

@@ -0,0 +1,4 @@
+
+config  BOARD_ALTERA_MAX10
+        bool "Altera MAX10 Board"
+        depends on SOC_NIOS2E_ZEPHYR

boards/altera_max10/Kconfig.defconfig

@@ -0,0 +1,7 @@
+if BOARD_ALTERA_MAX10
+
+config BOARD
+	default "altera_max10"
+
+endif
+

boards/altera_max10/Makefile

@@ -0,0 +1,5 @@
+ccflags-y += -I$(srctree)/include/drivers
+ccflags-y += -I$(srctree)/drivers
+asflags-y := ${ccflags-y}
+
+obj-y += board.o

boards/altera_max10/altera_max10_defconfig

@@ -0,0 +1,10 @@
+CONFIG_NIOS2=y
+CONFIG_SOC_NIOS2E_ZEPHYR=y
+CONFIG_BOARD_ALTERA_MAX10=y
+
+# Totally bogus values, fix later
+CONFIG_SRAM_BASE_ADDRESS=0x10000000
+CONFIG_SRAM_SIZE=64
+CONFIG_FLASH_BASE_ADDRESS=0x20000000
+CONFIG_FLASH_SIZE=64
+

boards/altera_max10/board.c

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011-2015, Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include "board.h"
+#include <uart.h>
+#include <device.h>
+#include <init.h>

boards/altera_max10/board.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+#endif /* __INC_BOARD_H */

drivers/timer/Kconfig

@@ -141,6 +141,15 @@ config CORTEX_M_SYSTICK
 	This module implements a kernel device driver for the Cortex-M processor
 	SYSTICK timer and provides the standard "system clock driver" interfaces.
 
+config NIOS2_AVALON_TIMER
+	bool "Nios II Avalon Interval Timer"
+	default y
+	depends on NIOS2
+	help
+	This module implements a kernel device driver for the Nios II Avalon
+	Interval Timer as described in the Embedded IP documentation. It
+	provides the standard "system clock driver" interfaces.
+
 config SYSTEM_CLOCK_DISABLE
 	bool "API to disable system clock"
 	default n

drivers/timer/Makefile

@@ -1,6 +1,7 @@
 obj-$(CONFIG_HPET_TIMER) += hpet.o
 obj-$(CONFIG_LOAPIC_TIMER) += loapic_timer.o
 obj-$(CONFIG_ARCV2_TIMER) += arcv2_timer0.o
+obj-$(CONFIG_NIOS2_AVALON_TIMER) += nios2_avalon_timer.o
 
 _CORTEX_M_SYSTICK_AND_GDB_INFO_yy = y
 obj-$(CONFIG_CORTEX_M_SYSTICK) += cortex_m_systick.o

drivers/timer/nios2_avalon_timer.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <arch/cpu.h>
+#include <device.h>
+
+int _sys_clock_driver_init(struct device *device)
+{
+	ARG_UNUSED(device);
+
+	/* STUB */
+
+	return 0;
+}
+
+/**
+ *
+ * @brief Read the platform's timer hardware
+ *
+ * This routine returns the current time in terms of timer hardware clock
+ * cycles.
+ *
+ * @return up counter of elapsed clock cycles
+ */
+uint32_t sys_cycle_get_32(void)
+{
+	/* STUB */
+	return 0;
+}
+

include/arch/cpu.h

@@ -25,6 +25,8 @@
 #include <arch/arm/arch.h>
 #elif defined(CONFIG_ARC)
 #include <arch/arc/arch.h>
+#elif defined(CONFIG_NIOS2)
+#include <arch/nios2/arch.h>
 #else
 #error "Unknown Architecture"
 #endif

include/arch/nios2/arch.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Nios II specific nanokernel interface header
+ * This header contains the Nios II specific nanokernel interface.  It is
+ * included by the generic nanokernel interface header (nanokernel.h)
+ */
+
+#ifndef _ARCH_IFACE_H
+#define _ARCH_IFACE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STACK_ALIGN  4
+
+#define _NANO_ERR_HW_EXCEPTION (0)      /* MPU/Bus/Usage fault */
+#define _NANO_ERR_INVALID_TASK_EXIT (1) /* Invalid task exit */
+#define _NANO_ERR_STACK_CHK_FAIL (2)    /* Stack corruption detected */
+#define _NANO_ERR_ALLOCATION_FAIL (3)   /* Kernel Allocation Failure */
+
+#ifndef _ASMLANGUAGE
+#include <stdint.h>
+#include <irq.h>
+#include <arch/nios2/asm_inline.h>
+
+/* STUB. Eventually port ARC/ARM interrupt stuff */
+#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p)
+
+static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
+{
+	/* STUB */
+
+	return 0;
+}
+
+static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
+{
+	/* STUB */
+	ARG_UNUSED(key);
+}
+
+int _arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
+			      void (*routine)(void *parameter), void *parameter,
+			      uint32_t flags);
+void _arch_irq_enable(unsigned int irq);
+void _arch_irq_disable(unsigned int irq);
+
+struct __esf {
+	/* XXX - not defined yet */
+	uint32_t placeholder;
+};
+
+typedef struct __esf NANO_ESF;
+extern const NANO_ESF _default_esf;
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

include/arch/nios2/asm_inline.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ASM_INLINE_PUBLIC_H
+#define _ASM_INLINE_PUBLIC_H
+
+/*
+ * The file must not be included directly
+ * Include nanokernel/cpu.h instead
+ */
+
+#if defined(__GNUC__)
+#include <arch/nios2/asm_inline_gcc.h>
+#else
+#include <arch/nios2/asm_inline_other.h>
+#endif
+
+#endif /* _ASM_INLINE_PUBLIC_H */

include/arch/nios2/asm_inline_gcc.h

@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ASM_INLINE_GCC_H
+#define _ASM_INLINE_GCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * The file must not be included directly
+ * Include arch/cpu.h instead
+ */
+
+#ifndef _ASMLANGUAGE
+
+#include <sys_io.h>
+
+/**
+ *
+ * @brief find most significant bit set in a 32-bit word
+ *
+ * This routine finds the first bit set starting from the most significant bit
+ * in the argument passed in and returns the index of that bit.  Bits are
+ * numbered starting at 1 from the least significant bit.  A return value of
+ * zero indicates that the value passed is zero.
+ *
+ * @return most significant bit set, 0 if @a op is 0
+ */
+
+static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
+{
+	ARG_UNUSED(op);
+	/* STUB */
+	return 0;
+}
+
+/**
+ *
+ * @brief find least significant bit set in a 32-bit word
+ *
+ * This routine finds the first bit set starting from the least significant bit
+ * in the argument passed in and returns the index of that bit.  Bits are
+ * numbered starting at 1 from the least significant bit.  A return value of
+ * zero indicates that the value passed is zero.
+ *
+ * @return least significant bit set, 0 if @a op is 0
+ */
+
+static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
+{
+	ARG_UNUSED(op);
+	/* STUB */
+	return 0;
+}
+
+/* Implementation of sys_io.h's documented functions */
+
+static inline __attribute__((always_inline))
+	void sys_out8(uint8_t data, io_port_t port)
+{
+	ARG_UNUSED(data);
+	ARG_UNUSED(port);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	uint8_t sys_in8(io_port_t port)
+{
+	ARG_UNUSED(port);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	void sys_out16(uint16_t data, io_port_t port)
+{
+	ARG_UNUSED(data);
+	ARG_UNUSED(port);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	uint16_t sys_in16(io_port_t port)
+{
+	ARG_UNUSED(port);
+	/* STUB */
+	return 0;
+
+}
+
+static inline __attribute__((always_inline))
+	void sys_out32(uint32_t data, io_port_t port)
+{
+	ARG_UNUSED(data);
+	ARG_UNUSED(port);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	uint32_t sys_in32(io_port_t port)
+{
+	ARG_UNUSED(port);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	void sys_io_set_bit(io_port_t port, unsigned int bit)
+{
+	ARG_UNUSED(port);
+	ARG_UNUSED(bit);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	void sys_io_clear_bit(io_port_t port, unsigned int bit)
+{
+	ARG_UNUSED(port);
+	ARG_UNUSED(bit);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	int sys_io_test_bit(io_port_t port, unsigned int bit)
+{
+	ARG_UNUSED(port);
+	ARG_UNUSED(bit);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
+{
+	ARG_UNUSED(port);
+	ARG_UNUSED(bit);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit)
+{
+	ARG_UNUSED(port);
+	ARG_UNUSED(bit);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	void sys_write8(uint8_t data, mm_reg_t addr)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(data);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	uint8_t sys_read8(mm_reg_t addr)
+{
+	ARG_UNUSED(addr);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	void sys_write16(uint16_t data, mm_reg_t addr)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(data);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	uint16_t sys_read16(mm_reg_t addr)
+{
+	ARG_UNUSED(addr);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	void sys_write32(uint32_t data, mm_reg_t addr)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(data);
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	uint32_t sys_read32(mm_reg_t addr)
+{
+	ARG_UNUSED(addr);
+	/* STUB */
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	void sys_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	void sys_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	int sys_test_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+}
+
+static inline __attribute__((always_inline))
+	void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+
+}
+
+static inline __attribute__((always_inline))
+	int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	int sys_bitfield_test_and_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+
+	return 0;
+}
+
+static inline __attribute__((always_inline))
+	int sys_bitfield_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(bit);
+
+	/* STUB */
+
+	return 0;
+}
+
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASM_INLINE_GCC_PUBLIC_GCC_H */

include/linker-defs.h

@@ -39,6 +39,8 @@
 /* Nothing yet to include */
 #elif defined(CONFIG_ARC)
 /* Nothing yet to include */
+#elif defined(CONFIG_NIOS2)
+/* Nothing yet to include */
 #else
 #error Arch not supported.
 #endif

include/linker-tool-gcc.h

@@ -37,6 +37,8 @@
 		OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
 		OUTPUT_ARCH(i386)
 	#endif
+#elif defined(CONFIG_NIOS2)
+	OUTPUT_FORMAT("elf32-littlenios2", "elf32-bignios2", "elf32-littlenios2")
 #else
 	#error Arch not supported.
 #endif

include/toolchain/gcc.h

@@ -273,6 +273,14 @@ A##a:
 		",%c0"                              \
 		"\n\t.type\t" #name ",@object" :  : "n"(value))
 
+#elif defined(CONFIG_NIOS2)
+
+/* No special prefixes necessary for constants in this arch AFAICT */
+#define GEN_ABSOLUTE_SYM(name, value)		\
+	__asm__(".globl\t" #name "\n\t.equ\t" #name \
+		",%0"                              \
+		"\n\t.type\t" #name ",%%object" :  : "n"(value))
+
 #else
 #error processor architecture not supported
 #endif

lib/libc/minimal/include/bits/size_t.h

@@ -28,6 +28,8 @@ typedef unsigned long int size_t;
 typedef unsigned int size_t;
 #elif defined(__arc__)
 typedef unsigned int size_t;
+#elif defined(__NIOS2__)
+typedef unsigned int size_t;
 #else
 #error "The minimal libc library does not recognize the architecture!\n"
 #endif

lib/libc/minimal/include/sys/types.h

@@ -26,6 +26,8 @@ typedef long int ssize_t;
 typedef int ssize_t;
 #elif defined(__arc__)
 typedef int ssize_t;
+#elif defined(__NIOS2__)
+typedef int ssize_t;
 #else
 #error "The minimal libc library does not recognize the architecture!\n"
 #endif
@@ -41,6 +43,8 @@ typedef long int off_t;
 typedef int off_t;
 #elif defined(__arc__)
 typedef int off_t;
+#elif defined(__NIOS2__)
+typedef int off_t;
 #else
 #error "The minimal libc library does not recognize the architecture!\n"
 #endif