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stm32: clean up after completion of transition to ll Clock control

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Following migration of stm32f1xx series clock control driver to
STM32Cube LL API, cleanup stm32 code base in order to take into
account that this is the only clock driver available for stm32
family.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-06-01 17:49:20 +02:00 • committed by Anas Nashif
commit 9413c8ba4d
22 changed files with 5 additions and 138 deletions
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1
arch/arm/soc/st_stm32/stm32f1/Kconfig.series
View file

@ -13,5 +13,6 @@ config SOC_SERIES_STM32F1X
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
select HAS_STM32CUBE
select CPU_HAS_SYSTICK
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for STM32F1 MCU series

1
arch/arm/soc/st_stm32/stm32f3/Kconfig.series
View file

@ -14,5 +14,6 @@ config SOC_SERIES_STM32F3X
select CPU_HAS_FPU
select CPU_HAS_SYSTICK
select HAS_STM32CUBE
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for STM32F3 MCU series

7
arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
View file

@ -28,13 +28,6 @@ config UART_STM32
endif #SERIAL
if CLOCK_CONTROL
config CLOCK_CONTROL_STM32_CUBE
def_bool y
endif #CLOCK_CONTROL
if GPIO
config GPIO_STM32

1
arch/arm/soc/st_stm32/stm32f4/Kconfig.series
View file

@ -15,5 +15,6 @@ config SOC_SERIES_STM32F4X
select HAS_STM32CUBE
select CPU_HAS_MPU
select CPU_HAS_SYSTICK
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for STM32F4 MCU series

1
arch/arm/soc/st_stm32/stm32l4/Kconfig.series
View file

@ -13,5 +13,6 @@ config SOC_SERIES_STM32L4X
select SOC_FAMILY_STM32
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
select CPU_HAS_SYSTICK
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for STM32L4 MCU series

1
boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig
View file

@ -21,7 +21,6 @@ CONFIG_GPIO_STM32=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration

1
boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig
View file

@ -31,7 +31,6 @@ CONFIG_GPIO_STM32_PORTC=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input

1
boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig
View file

@ -41,7 +41,6 @@ CONFIG_GPIO_STM32_PORTC=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# HSE configuration

1
boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig
View file

@ -26,7 +26,6 @@ CONFIG_GPIO_STM32_PORTH=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration

1
boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig
View file

@ -30,7 +30,6 @@ CONFIG_GPIO_STM32_PORTH=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration

1
boards/arm/olimexino_stm32/olimexino_stm32_defconfig
View file

@ -33,7 +33,6 @@ CONFIG_GPIO_STM32_PORTD=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input

1
boards/arm/stm3210c_eval/stm3210c_eval_defconfig
View file

@ -43,7 +43,6 @@ CONFIG_GPIO_STM32_PORTC=y
# RCC configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input

1
boards/arm/stm32373c_eval/stm32373c_eval_defconfig
View file

@ -50,7 +50,6 @@ CONFIG_GPIO_STM32_PORTE=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# HSE configuration

1
boards/arm/stm32_mini_a15/stm32_mini_a15_defconfig
View file

@ -24,7 +24,6 @@ CONFIG_GPIO_STM32_PORTB=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input

1
boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig
View file

@ -30,7 +30,6 @@ CONFIG_GPIO_STM32_PORTH=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration

39
drivers/gpio/gpio_stm32.c
View file

@ -188,18 +188,12 @@ static int gpio_stm32_init(struct device *device)
struct device *clk =
device_get_binding(STM32_CLOCK_CONTROL_NAME);
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken);
#else
clock_control_on(clk, cfg->clock_subsys);
#endif
return 0;
}
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr, __bus) \
static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
.base = (u32_t *)__base_addr, \
@ -216,30 +210,7 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&gpio_stm32_driver);
#else
/* TODO: This case only applies to F1 family */
/* To be removed when migrated to LL clock control driver */
#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __clock) \
static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
.base = (u32_t *)__base_addr, \
.port = __port, \
.clock_subsys = UINT_TO_POINTER(__clock) \
}; \
static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
__name, \
gpio_stm32_init, \
&gpio_stm32_data_## __suffix, \
&gpio_stm32_cfg_## __suffix, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&gpio_stm32_driver);
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#ifdef CONFIG_SOC_SERIES_STM32F1X
/* On STM32F1 series, AFIO should be clocked to access GPIOs */
#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \
@ -255,14 +226,6 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
STM32_PERIPH_GPIO##__SUFFIX, \
STM32_CLOCK_BUS_GPIO)
#endif /* CONFIG_SOC_SERIES_STM32F1X */
#else
/* TODO: Clean once F1 series moved to LL Clock control */
#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \
GPIO_DEVICE_INIT("GPIO" #__SUFFIX, __suffix, \
GPIO##__SUFFIX##_BASE, STM32_PORT##__SUFFIX, \
STM32F10X_CLOCK_SUBSYS_IOP##__SUFFIX | \
STM32F10X_CLOCK_SUBSYS_AFIO)
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#ifdef CONFIG_GPIO_STM32_PORTA
GPIO_DEVICE_INIT_STM32(a, A);

7
drivers/gpio/gpio_stm32.h
View file

@ -16,7 +16,6 @@
#include <gpio.h>
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
/* GPIO buses definitions */
#ifdef CONFIG_SOC_SERIES_STM32F1X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_APB2
@ -48,7 +47,6 @@
#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
#endif /* CONFIG_SOC_SERIES_.. */
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
@ -60,12 +58,7 @@ struct gpio_stm32_config {
u32_t *base;
/* IO port */
enum stm32_pin_port port;
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
struct stm32_pclken pclken;
#else /* SOC_SERIES_STM32F1X */
/* clock subsystem */
clock_control_subsys_t clock_subsys;
#endif
};
/**

10
drivers/pinmux/stm32/pinmux_stm32.c
View file

@ -23,7 +23,6 @@
#include "pinmux.h"
#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
static const u32_t ports_enable[STM32_PORTS_MAX] = {
STM32_PERIPH_GPIOA,
STM32_PERIPH_GPIOB,
@ -44,7 +43,6 @@ static const u32_t ports_enable[STM32_PORTS_MAX] = {
STM32_PERIPH_GPIOH,
#endif
};
#endif
/**
* @brief enable IO port clock
@ -61,20 +59,12 @@ static int enable_port(u32_t port, struct device *clk)
clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
}
/* TODO: Merge this and move the port clock to the soc file */
#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
struct stm32_pclken pclken;
pclken.bus = STM32_CLOCK_BUS_GPIO;
pclken.enr = ports_enable[port];
return clock_control_on(clk, (clock_control_subsys_t *) &pclken);
#else
/* TODO: Clean once F1 series moved to LL Clock control */
clock_control_subsys_t subsys = stm32_get_port_clock(port);
return clock_control_on(clk, subsys);
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
}
static int stm32_pin_configure(int pin, int func, int altf)

48
drivers/pwm/pwm_stm32.c
View file

@ -24,14 +24,8 @@
#define PWM_STRUCT(dev) \
((TIM_TypeDef *)(DEV_CFG(dev))->pwm_base)
#ifdef CONFIG_SOC_SERIES_STM32F1X
#define CLOCK_SUBSYS_TIM1 STM32F10X_CLOCK_SUBSYS_TIM1
#define CLOCK_SUBSYS_TIM2 STM32F10X_CLOCK_SUBSYS_TIM2
#endif
#define CHANNEL_LENGTH 4
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
static u32_t __get_tim_clk(u32_t bus_clk,
clock_control_subsys_t *sub_system)
{
@ -52,30 +46,6 @@ static u32_t __get_tim_clk(u32_t bus_clk,
return tim_clk;
}
#else
/* This code only applies to F1 family */
/* To be deleted when F1 series ported to LL clock control driver */
static u32_t __get_tim_clk(u32_t bus_clk,
clock_control_subsys_t sub_system)
{
u32_t tim_clk, apb_psc;
u32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
apb_psc = CONFIG_CLOCK_STM32F10X_APB2_PRESCALER;
} else {
apb_psc = CONFIG_CLOCK_STM32F10X_APB1_PRESCALER;
}
if (apb_psc == RCC_HCLK_DIV1) {
tim_clk = bus_clk;
} else {
tim_clk = 2 * bus_clk;
}
return tim_clk;
}
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
/*
* Set the period and pulse width for a PWM pin.
@ -177,17 +147,11 @@ static int pwm_stm32_get_cycles_per_sec(struct device *dev, u32_t pwm,
}
/* Timer clock depends on APB prescaler */
#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
clock_control_get_rate(data->clock,
(clock_control_subsys_t *)&cfg->pclken, &bus_clk);
tim_clk = __get_tim_clk(bus_clk,
(clock_control_subsys_t *)&cfg->pclken);
#else
clock_control_get_rate(data->clock, cfg->clock_subsys, &bus_clk);
tim_clk = __get_tim_clk(bus_clk, cfg->clock_subsys);
#endif
*cycles = (u64_t)(tim_clk / (data->pwm_prescaler + 1));
@ -219,12 +183,8 @@ static int pwm_stm32_init(struct device *dev)
__pwm_stm32_get_clock(dev);
/* enable clock */
#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
clock_control_on(data->clock,
(clock_control_subsys_t *)&config->pclken);
#else
clock_control_on(data->clock, config->clock_subsys);
#endif
return 0;
}
@ -238,12 +198,8 @@ static struct pwm_stm32_data pwm_stm32_dev_data_1 = {
static const struct pwm_stm32_config pwm_stm32_dev_cfg_1 = {
.pwm_base = TIM1_BASE,
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
.pclken = { .bus = STM32_CLOCK_BUS_APB2,
.enr = LL_APB2_GRP1_PERIPH_TIM1 },
#else
.clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM1),
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
};
DEVICE_AND_API_INIT(pwm_stm32_1, CONFIG_PWM_STM32_1_DEV_NAME,
@ -262,12 +218,8 @@ static struct pwm_stm32_data pwm_stm32_dev_data_2 = {
static const struct pwm_stm32_config pwm_stm32_dev_cfg_2 = {
.pwm_base = TIM2_BASE,
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
.pclken = { .bus = STM32_CLOCK_BUS_APB1,
.enr = LL_APB1_GRP1_PERIPH_TIM2 },
#else
.clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM2),
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
};
DEVICE_AND_API_INIT(pwm_stm32_2, CONFIG_PWM_STM32_2_DEV_NAME,

4
drivers/pwm/pwm_stm32.h
View file

@ -19,11 +19,7 @@ extern "C" {
struct pwm_stm32_config {
u32_t pwm_base;
/* clock subsystem driving this peripheral */
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
struct stm32_pclken pclken;
#else
clock_control_subsys_t clock_subsys;
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
};
/** Runtime driver data */

10
drivers/serial/uart_stm32.c
View file

@ -280,12 +280,8 @@ static int uart_stm32_init(struct device *dev)
__uart_stm32_get_clock(dev);
/* enable clock */
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
clock_control_on(data->clock,
(clock_control_subsys_t *)&config->pclken);
#else
clock_control_on(data->clock, config->clock_subsys);
#endif
UartHandle->Instance = UART_STRUCT(dev);
UartHandle->Init.WordLength = UART_WORDLENGTH_8B;
@ -304,15 +300,9 @@ static int uart_stm32_init(struct device *dev)
}
/* Define clocks */
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#define STM32_CLOCK_UART(type, apb, n) \
.pclken = { .bus = STM32_CLOCK_BUS_ ## apb, \
.enr = LL_##apb##_GRP1_PERIPH_##type##n }
#else
#define STM32_CLOCK_UART(type, apb, n) \
.clock_subsys = UINT_TO_POINTER( \
STM32F10X_CLOCK_SUBSYS_##type##n)
#endif /* CLOCK_CONTROL_STM32_CUBE */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
#define STM32_UART_IRQ_HANDLER_DECL(n) \

4
drivers/serial/uart_stm32.h
View file

@ -16,11 +16,7 @@
struct uart_stm32_config {
struct uart_device_config uconf;
/* clock subsystem driving this peripheral */
#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
struct stm32_pclken pclken;
#else
clock_control_subsys_t clock_subsys;
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
};
/* driver data */