From 93c005de3ef5c10367cb2e0656db0f91da123750 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Wed, 23 Jun 2021 13:30:12 +0200 Subject: [PATCH] dts/arm/st: Add stm32u5 base and initial device Add initial basic description for Cortex-M33 based stm32u5 soc series. This encompass description for base nodes, such as: - cpu - flash - clocks - sram Additionally, provide description for variant stm32u575Xi. Related to clocks nodes, added bindings for stm32u5 specific rcc node as well as msi and pll clocks. Header file stm32_clock_control.h was also updated to support these new bindings. Note that for compatibility with existing definitions, clock node describing main pll clock, known as "PLL1", was given two labels: "pll" and "pll1". Signed-off-by: Erwan Gouriou --- dts/arm/st/u5/stm32u5.dtsi | 105 ++++++++++++++++++ dts/arm/st/u5/stm32u575.dtsi | 7 ++ dts/arm/st/u5/stm32u575Xi.dtsi | 21 ++++ dts/bindings/clock/st,stm32u5-msi-clock.yaml | 37 ++++++ dts/bindings/clock/st,stm32u5-pll-clock.yaml | 67 +++++++++++ dts/bindings/clock/st,stm32u5-rcc.yaml | 22 ++++ .../clock_control/stm32_clock_control.h | 22 +++- 7 files changed, 278 insertions(+), 3 deletions(-) create mode 100644 dts/arm/st/u5/stm32u5.dtsi create mode 100644 dts/arm/st/u5/stm32u575.dtsi create mode 100644 dts/arm/st/u5/stm32u575Xi.dtsi create mode 100644 dts/bindings/clock/st,stm32u5-msi-clock.yaml create mode 100644 dts/bindings/clock/st,stm32u5-pll-clock.yaml create mode 100644 dts/bindings/clock/st,stm32u5-rcc.yaml diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi new file mode 100644 index 00000000000..d58da175a1b --- /dev/null +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <8>; + }; + }; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "st,stm32-hse-clock"; + status = "disabled"; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_msis: clk-msis { + #clock-cells = <0>; + compatible = "st,stm32u5-msi-clock"; + msi-range = <4>; /* 4MHz (reset value) */ + status = "disabled"; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + status = "disabled"; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + + pll1: pll: pll { + #clock-cells = <0>; + compatible = "st,stm32u5-pll-clock"; + status = "disabled"; + }; + }; + + soc { + flash-controller@40022000 { + compatible = "st,stm32u5-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x40022000 0x400>; + interrupts = <6 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + label = "FLASH_STM32"; + }; + }; + + rcc: rcc@46020c00 { + compatible = "st,stm32u5-rcc"; + clocks-controller; + #clock-cells = <2>; + reg = <0x46020c00 0x400>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/u5/stm32u575.dtsi b/dts/arm/st/u5/stm32u575.dtsi new file mode 100644 index 00000000000..c4056857811 --- /dev/null +++ b/dts/arm/st/u5/stm32u575.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/st/u5/stm32u575Xi.dtsi b/dts/arm/st/u5/stm32u575Xi.dtsi new file mode 100644 index 00000000000..652493cc566 --- /dev/null +++ b/dts/arm/st/u5/stm32u575Xi.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(786)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_M(2)>; + }; + }; + }; +}; diff --git a/dts/bindings/clock/st,stm32u5-msi-clock.yaml b/dts/bindings/clock/st,stm32u5-msi-clock.yaml new file mode 100644 index 00000000000..52398b3f5d6 --- /dev/null +++ b/dts/bindings/clock/st,stm32u5-msi-clock.yaml @@ -0,0 +1,37 @@ +# Copyright (c) 2021, Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +description: STM32U5 Multi Speed Internal Clock + +compatible: "st,stm32u5-msi-clock" + +include: + - name: st,stm32-msi-clock.yaml + property-blocklist: + - msi-range + +properties: + + msi-range: + default: 4 + required: true + type: int + description: | + MSI clock ranges + enum: + - 0 # range 0 around 48 MHz + - 1 # range 1 around 24 MHz + - 2 # range 2 around 16 MHz + - 3 # range 3 around 12 MHz + - 4 # range 4 around 4 MHz (reset value) + - 5 # range 5 around 2 MHz + - 6 # range 6 around 1.33 MHz + - 7 # range 7 around 1 MHz + - 8 # range 8 around 3.072 MHz + - 9 # range 9 around 1.536 MHz + - 10 # range 10 around 1.024 MHz + - 11 # range 11 around 768 KHz + - 12 # range 12 around 400 KHz + - 13 # range 13 around 200 KHz + - 14 # range 14 around 133 KHz + - 15 # range 14 around 100 KHz diff --git a/dts/bindings/clock/st,stm32u5-pll-clock.yaml b/dts/bindings/clock/st,stm32u5-pll-clock.yaml new file mode 100644 index 00000000000..6e2fb6db4fd --- /dev/null +++ b/dts/bindings/clock/st,stm32u5-pll-clock.yaml @@ -0,0 +1,67 @@ +# Copyright (c) 2021, Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +description: | + PLL node binding for STM32U5 devices + + It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3. + Only main PLL (PLL1) is supported for now. + + These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with + an input frequency from 4 to 16 MHz. PLLM factor is used to set the input + clock in this acceptable range. + + Each PLL can have up to 3 output clocks and for each output clock, the + frequency can be computed with the following formulae: + + f(PLL_P) = f(VCO clock) / PLLP + f(PLL_Q) = f(VCO clock) / PLLQ + f(PLL_R) = f(VCO clock) / PLLR + + with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) + + Note: To reduce the power consumption, it is recommended to configure the VCOx + clock output to the lowest frequency. + + The PLL output frequency must not exceed 160 MHz. + +compatible: "st,stm32u5-pll-clock" + +include: [clock-controller.yaml, base.yaml] + +properties: + + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Prescaler for PLLx + input clock + Valid range: 1 - 16 + + mul-n: + type: int + required: true + description: | + PLLx multiplication factor for VCO + Valid range: 4 - 512 + + div-q: + type: int + required: false + description: | + PLLx DIVQ division factor + Valid range: 2 - 128 + + div-r: + type: int + required: true + description: | + PLLx DIVR division factor + Valid range: 2 - 128 diff --git a/dts/bindings/clock/st,stm32u5-rcc.yaml b/dts/bindings/clock/st,stm32u5-rcc.yaml new file mode 100644 index 00000000000..88a31b0901e --- /dev/null +++ b/dts/bindings/clock/st,stm32u5-rcc.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2021, Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +description: | + STM32U5 Reset and Clock controller node. + For more description confere st,stm32-rcc.yaml + +compatible: "st,stm32u5-rcc" + +include: st,stm32-rcc.yaml + +properties: + + apb3-prescaler: + type: int + required: false + enum: + - 1 + - 2 + - 4 + - 8 + - 16 diff --git a/include/drivers/clock_control/stm32_clock_control.h b/include/drivers/clock_control/stm32_clock_control.h index fe778eaf4cb..de7cc121db6 100644 --- a/include/drivers/clock_control/stm32_clock_control.h +++ b/include/drivers/clock_control/stm32_clock_control.h @@ -88,7 +88,8 @@ #endif #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), ahb_prescaler) || \ - DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), ahb_prescaler) + DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), ahb_prescaler) || \ + DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), ahb_prescaler) #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler) #else #define STM32_AHB_PRESCALER CONFIG_CLOCK_STM32_AHB_PRESCALER @@ -96,6 +97,7 @@ #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb1_prescaler) || \ DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), apb1_prescaler) || \ + DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb1_prescaler) || \ DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb1_prescaler) || \ DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb1_prescaler) #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler) @@ -104,6 +106,7 @@ #endif #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb2_prescaler) || \ + DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb2_prescaler) || \ DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb2_prescaler) || \ DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb2_prescaler) #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler) @@ -112,6 +115,10 @@ #define STM32_APB2_PRESCALER CONFIG_CLOCK_STM32_APB2_PRESCALER #endif +#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb3_prescaler) +#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler) +#endif + #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), ahb3_prescaler) #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler) #else @@ -161,6 +168,7 @@ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) @@ -223,6 +231,7 @@ #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) || \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32u5_rcc, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wb_rcc, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wl_rcc, okay)) && \ DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) @@ -252,10 +261,12 @@ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay)) && \ DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks) #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll)) #define STM32_PLL_SRC_MSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) +#define STM32_PLL_SRC_MSIS DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) #define STM32_PLL_SRC_HSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) #define STM32_PLL_SRC_HSE DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) #define STM32_PLL_SRC_PLL2 DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2)) @@ -275,16 +286,21 @@ #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay) #define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range) -#else +#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) #define STM32_MSI_RANGE CONFIG_CLOCK_STM32_MSI_RANGE #endif #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) #define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode) -#else +#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) #define STM32_MSI_PLL_MODE CONFIG_CLOCK_STM32_MSI_PLL_MODE #endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) +#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range) +#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode) +#endif + #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) #define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div) #else