soc: add wch_ch32v003 soc files

This commit adds the soc support for WCH CH32V003.

Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

soc/wch/ch32v00x/CMakeLists.txt

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc_irq.S
+  vector.S
+)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/wch/ch32v00x/Kconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_CH32V003
+	select RISCV
+	select BUILD_OUTPUT_HEX
+	select RISCV_ISA_RV32E
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_ISA_EXT_C
+	select CH32V00X_SYSTICK
+	select ATOMIC_OPERATIONS_C
+	imply XIP

soc/wch/ch32v00x/Kconfig.defconfig

@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_CH32V003
+
+config NUM_IRQS
+	default 48
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config MAIN_STACK_SIZE
+	default 512
+
+config IDLE_STACK_SIZE
+	default 256
+
+config ISR_STACK_SIZE
+	default 256
+
+config CLOCK_CONTROL
+	default y
+
+endif # SOC_CH32V003

soc/wch/ch32v00x/Kconfig.soc

@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_CH32V00X
+	bool
+
+config SOC_CH32V003
+	bool
+	select SOC_SERIES_CH32V00X
+
+config SOC_SERIES
+	default "ch32v00x" if SOC_SERIES_CH32V00X
+
+config SOC
+	default "ch32v003" if SOC_CH32V003

soc/wch/ch32v00x/soc.yml

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+series:
+  - name: ch32v00x
+    socs:
+      - name: ch32v003

soc/wch/ch32v00x/soc_irq.S

@@ -0,0 +1,19 @@
+/* Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <offsets.h>
+#include <zephyr/toolchain.h>
+
+/* Exports */
+GTEXT(__soc_is_irq)
+GTEXT(__soc_handle_irq)
+
+SECTION_FUNC(exception.other, __soc_is_irq)
+	csrr a0, mcause
+	srli a0, a0, 31
+	ret
+
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	ret

soc/wch/ch32v00x/vector.S

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+/* Exports */
+GTEXT(__start)
+
+/* Imports */
+GTEXT(__initialize)
+
+SECTION_FUNC(vectors, ivt)
+	.option norvc
+	j       __start
+	.rept 38
+	.word	_isr_wrapper
+	.endr
+
+SECTION_FUNC(vectors, __start)
+	li 	a0, 3
+	csrw	mtvec, a0
+	j	__initialize