michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: flash: stm32 qspi Enter 4-Byte Address Mode

Browse source 
No need to read back the CR (NOR flash config or control register)
to check if entering the 4-Byte Address Mode is effective.
The action of this command is immediate and the result
(bit field of the CR) is NOR flash vendor-specific.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2023-02-22 11:51:46 +01:00 • committed by Carles Cufí
commit 9363a9319e
2 changed files with 6 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

25
drivers/flash/flash_stm32_qspi.c
View file

@ -719,34 +719,21 @@ static int setup_pages_layout(const struct device *dev)
static int qspi_program_addr_4b(const struct device *dev) static int qspi_program_addr_4b(const struct device *dev)
{ {
uint8_t reg;
int ret;
/* Program the flash memory to use 4 bytes addressing */ /* Program the flash memory to use 4 bytes addressing */
QSPI_CommandTypeDef cmd = { QSPI_CommandTypeDef cmd = {
.Instruction = SPI_NOR_CMD_4BA, .Instruction = SPI_NOR_CMD_4BA,
.InstructionMode = QSPI_INSTRUCTION_1_LINE, .InstructionMode = QSPI_INSTRUCTION_1_LINE,
}; };
ret = qspi_send_cmd(dev, &cmd);
if (ret) {
return ret;
}
/* /*
* Read control register to verify if 4byte addressing mode * No need to Read control register afterwards to verify if 4byte addressing mode
* is enabled. * is enabled as the effect of the command is immediate
* and the SPI_NOR_CMD_RDCR is vendor-specific :
* SPI_NOR_4BYTE_BIT is BIT 5 for Macronix and 0 for Micron or Windbond
* Moreover bit value meaning is also vendor-specific
*/ */
cmd.Instruction = SPI_NOR_CMD_RDCR;
cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
cmd.DataMode = QSPI_DATA_1_LINE;
ret = qspi_read_access(dev, &cmd, &reg, sizeof(reg)); return qspi_send_cmd(dev, &cmd);
if (!ret && !(reg & SPI_NOR_4BYTE_BIT)) {
return -EINVAL;
}
return ret;
} }
static int qspi_read_status_register(const struct device *dev, uint8_t reg_num, uint8_t *reg) static int qspi_read_status_register(const struct device *dev, uint8_t reg_num, uint8_t *reg)

3
drivers/flash/spi_nor.h
View file

@ -15,9 +15,6 @@
#define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */ #define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
#define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */ #define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */
/* Control register bits */
#define SPI_NOR_4BYTE_BIT BIT(5) /* 4B addressing */
/* Flash opcodes */ /* Flash opcodes */
#define SPI_NOR_CMD_WRSR 0x01 /* Write status register */ #define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
#define SPI_NOR_CMD_RDSR 0x05 /* Read status register */ #define SPI_NOR_CMD_RDSR 0x05 /* Read status register */