i2c: quark se: Add QMSI 1.1-based I2C shim driver
Add I2C QMSI shim driver for sensor system based on QMSI 1.1 Origin: Original Change-Id: I9c8efe49e8e9b7a5f8496fa49beb68e409148be7 Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Sergio Rodriguez
Anas Nashif
parent
862cff1eab
commit
92e9ffe481
4 changed files with 326 additions and 2 deletions
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@ -43,6 +43,25 @@ config I2C_QUARK_SE_SS
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This option enables the driver to support the I2C on Quark SE Sensor
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Subsystem.
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config I2C_QMSI_SS
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bool "QMSI I2C driver for the Sensor Subsystem"
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depends on I2C && QMSI
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default n
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help
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This option enable the Sensor QMSI I2C driver.
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This driver is simply a shim driver based on the I2C driver
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provided by the QMSI BSP.
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config I2C_QMSI_SS
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bool "QMSI I2C driver for the Sensor Subsystem"
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depends on QMSI && I2C
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default n
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help
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This option enable the Sensor QMSI I2C driver.
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This driver is simply a shim driver based on the I2C driver
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provided by the QMSI BSP.
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config I2C_QMSI
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bool "QMSI I2C driver"
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@ -1,5 +1,5 @@
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ccflags-$(CONFIG_I2C_QMSI) +=-I$(CONFIG_QMSI_INSTALL_PATH)/include
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obj-$(CONFIG_I2C_DW) += i2c_dw.o
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obj-$(CONFIG_I2C_QMSI) += i2c_qmsi.o
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obj-$(CONFIG_I2C_QMSI_SS) += i2c_qmsi_ss.o
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obj-$(CONFIG_I2C_QUARK_SE_SS) += i2c_quark_se_ss.o
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obj-$(CONFIG_I2C_ATMEL_SAM3) += i2c_atmel_sam3.o
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obj-$(CONFIG_I2C_ATMEL_SAM3) += i2c_atmel_sam3.o
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304
drivers/i2c/i2c_qmsi_ss.c
Normal file
304
drivers/i2c/i2c_qmsi_ss.c
Normal file
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@ -0,0 +1,304 @@
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/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <device.h>
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#include <i2c.h>
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#include <board.h>
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#include "qm_ss_i2c.h"
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#include "qm_ss_isr.h"
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#include "ss_clk.h"
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/* Convenient macros to get the controller instance and the driver data. */
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#define GET_CONTROLLER_INSTANCE(dev) \
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(((struct i2c_qmsi_ss_config_info *)dev->config->config_info)->instance)
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#define GET_DRIVER_DATA(dev) \
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((struct i2c_qmsi_ss_driver_data *)dev->driver_data)
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struct i2c_qmsi_ss_config_info {
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qm_ss_i2c_t instance; /* Controller instance. */
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union dev_config default_cfg;
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void (*irq_cfg)(void);
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};
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struct i2c_qmsi_ss_driver_data {
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device_sync_call_t sync;
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int transfer_status;
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};
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static int i2c_qmsi_ss_init(struct device *dev);
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static void i2c_qmsi_ss_isr(void *arg)
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{
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struct device *dev = arg;
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qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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if (instance == QM_SS_I2C_0) {
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qm_ss_i2c_isr_0(NULL);
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} else {
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qm_ss_i2c_isr_1(NULL);
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}
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}
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#ifdef CONFIG_I2C_0
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static struct i2c_qmsi_ss_driver_data driver_data_0;
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static void i2c_qmsi_ss_config_irq_0(void);
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static struct i2c_qmsi_ss_config_info config_info_0 = {
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.instance = QM_SS_I2C_0,
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.default_cfg.raw = CONFIG_I2C_0_DEFAULT_CFG,
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.irq_cfg = i2c_qmsi_ss_config_irq_0,
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};
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DEVICE_INIT(i2c_ss_0, CONFIG_I2C_0_NAME, i2c_qmsi_ss_init, &driver_data_0,
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&config_info_0, SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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static void i2c_qmsi_ss_config_irq_0(void)
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{
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uint32_t mask = 0;
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/* Need to unmask the interrupts in System Control Subsystem (SCSS)
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* so the interrupt controller can route these interrupts to
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* the sensor subsystem.
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*/
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_ERR_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_ERR_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_TX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_TX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_RX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_RX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_STOP_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_STOP_MASK);
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/* Connect the IRQs to ISR */
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IRQ_CONNECT(I2C_SS_0_ERR_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_0), 0);
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IRQ_CONNECT(I2C_SS_0_RX_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_0), 0);
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IRQ_CONNECT(I2C_SS_0_TX_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_0), 0);
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IRQ_CONNECT(I2C_SS_0_STOP_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_0), 0);
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irq_enable(I2C_SS_0_ERR_VECTOR);
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irq_enable(I2C_SS_0_RX_VECTOR);
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irq_enable(I2C_SS_0_TX_VECTOR);
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irq_enable(I2C_SS_0_STOP_VECTOR);
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}
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#endif /* CONFIG_I2C_0 */
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#ifdef CONFIG_I2C_1
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static struct i2c_qmsi_ss_driver_data driver_data_1;
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static void i2c_qmsi_ss_config_irq_1(void);
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static struct i2c_qmsi_ss_config_info config_info_1 = {
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.instance = QM_SS_I2C_1,
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.default_cfg.raw = CONFIG_I2C_1_DEFAULT_CFG,
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.irq_cfg = i2c_qmsi_ss_config_irq_1,
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};
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DEVICE_INIT(i2c_ss_1, CONFIG_I2C_1_NAME, i2c_qmsi_ss_init, &driver_data_1,
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&config_info_1, SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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static void i2c_qmsi_ss_config_irq_1(void)
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{
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uint32_t mask = 0;
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/* Need to unmask the interrupts in System Control Subsystem (SCSS)
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* so the interrupt controller can route these interrupts to
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* the sensor subsystem.
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*/
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_ERR_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_ERR_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_TX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_TX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_RX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_RX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_STOP_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_STOP_MASK);
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/* Connect the IRQs to ISR */
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IRQ_CONNECT(I2C_SS_1_ERR_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_1), 0);
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IRQ_CONNECT(I2C_SS_1_RX_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_1), 0);
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IRQ_CONNECT(I2C_SS_1_TX_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_1), 0);
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IRQ_CONNECT(I2C_SS_1_STOP_VECTOR, 1, i2c_qmsi_ss_isr,
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DEVICE_GET(i2c_ss_1), 0);
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irq_enable(I2C_SS_1_ERR_VECTOR);
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irq_enable(I2C_SS_1_RX_VECTOR);
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irq_enable(I2C_SS_1_TX_VECTOR);
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irq_enable(I2C_SS_1_STOP_VECTOR);
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}
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#endif /* CONFIG_I2C_1 */
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static int i2c_qmsi_ss_configure(struct device *dev, uint32_t config)
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{
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qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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union dev_config cfg;
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qm_ss_i2c_config_t qm_cfg;
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cfg.raw = config;
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/* This driver only supports master mode. */
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if (!cfg.bits.is_master_device) {
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return -EINVAL;
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}
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qm_cfg.address_mode = (cfg.bits.use_10_bit_addr) ? QM_SS_I2C_10_BIT :
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QM_SS_I2C_7_BIT;
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switch (cfg.bits.speed) {
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case I2C_SPEED_STANDARD:
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qm_cfg.speed = QM_SS_I2C_SPEED_STD;
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break;
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case I2C_SPEED_FAST:
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qm_cfg.speed = QM_SS_I2C_SPEED_FAST;
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break;
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default:
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return -EINVAL;
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}
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if (qm_ss_i2c_set_config(instance, &qm_cfg) != 0) {
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return -EIO;
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}
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return 0;
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}
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static void transfer_complete(void *data, int rc, qm_ss_i2c_status_t status,
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uint32_t len)
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{
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struct device *dev = data;
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struct i2c_qmsi_ss_driver_data *driver_data;
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driver_data = GET_DRIVER_DATA(dev);
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driver_data->transfer_status = rc;
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device_sync_call_complete(&driver_data->sync);
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}
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static int i2c_qmsi_ss_transfer(struct device *dev, struct i2c_msg *msgs,
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uint8_t num_msgs, uint16_t addr)
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{
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struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);
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qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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qm_ss_i2c_status_t status;
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int rc;
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qm_ss_i2c_get_status(instance, &status);
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if (status != QM_I2C_IDLE) {
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return -EBUSY;
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}
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if (msgs == NULL || num_msgs == 0) {
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return -ENOTSUP;
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}
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for (int i = 0; i < num_msgs; i++) {
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uint8_t *buf = msgs[i].buf;
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uint32_t len = msgs[i].len;
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uint8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
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bool stop = (msgs[i].flags & I2C_MSG_STOP) == I2C_MSG_STOP;
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qm_ss_i2c_transfer_t xfer = { 0 };
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if (op == I2C_MSG_WRITE) {
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xfer.tx = buf;
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xfer.tx_len = len;
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} else {
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xfer.rx = buf;
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xfer.rx_len = len;
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}
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xfer.callback = transfer_complete;
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xfer.callback_data = dev;
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xfer.stop = stop;
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rc = qm_ss_i2c_master_irq_transfer(instance, &xfer, addr);
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if (rc != 0)
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return -EIO;
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/* Block current thread until the I2C transfer completes. */
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if (stop || op != I2C_MSG_WRITE) {
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device_sync_call_wait(&driver_data->sync);
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if (driver_data->transfer_status != 0)
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return -EIO;
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}
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}
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return 0;
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}
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static int i2c_qmsi_ss_suspend(struct device *dev)
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{
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ARG_UNUSED(dev);
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return -ENODEV;
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}
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static int i2c_qmsi_ss_resume(struct device *dev)
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{
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ARG_UNUSED(dev);
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return -ENODEV;
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}
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static struct i2c_driver_api api = {
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.configure = i2c_qmsi_ss_configure,
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.transfer = i2c_qmsi_ss_transfer,
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.suspend = i2c_qmsi_ss_suspend,
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.resume = i2c_qmsi_ss_resume,
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};
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static int i2c_qmsi_ss_init(struct device *dev)
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{
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struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);
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struct i2c_qmsi_ss_config_info *config = dev->config->config_info;
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qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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int err;
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config->irq_cfg();
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ss_clk_i2c_enable(instance);
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err = i2c_qmsi_ss_configure(dev, config->default_cfg.raw);
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if (err < 0) {
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return err;
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}
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device_sync_call_init(&driver_data->sync);
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dev->driver_api = &api;
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return 0;
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}
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@ -17,3 +17,4 @@ obj-$(CONFIG_SOC_FLASH_QMSI) += drivers/qm_flash.o
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obj-$(CONFIG_PINMUX_DEV_QMSI) += drivers/qm_pinmux.o
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obj-$(CONFIG_SPI_QMSI_SS) += drivers/sensor/qm_ss_spi.o
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obj-$(CONFIG_GPIO_QMSI_SS) += drivers/sensor/qm_ss_gpio.o
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obj-$(CONFIG_I2C_QMSI_SS) += drivers/sensor/qm_ss_i2c.o
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