diff --git a/dts/arm/st/l1/stm32l1.dtsi b/dts/arm/st/l1/stm32l1.dtsi new file mode 100644 index 00000000000..acce0b9d306 --- /dev/null +++ b/dts/arm/st/l1/stm32l1.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019 Linaro Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m3"; + reg = <0>; + }; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + }; + + soc { + flash-controller@40023c00 { + compatible = "st,stm32l1-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x40023c00 0x400>; + interrupts = <4 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + label = "FLASH_STM32"; + + write-block-size = <4>; + }; + }; + + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/l1/stm32l151.dtsi b/dts/arm/st/l1/stm32l151.dtsi new file mode 100644 index 00000000000..264c0e7d328 --- /dev/null +++ b/dts/arm/st/l1/stm32l151.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2019 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/st/l1/stm32l151Xb.dtsi b/dts/arm/st/l1/stm32l151Xb.dtsi new file mode 100644 index 00000000000..971dd9b889a --- /dev/null +++ b/dts/arm/st/l1/stm32l151Xb.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(16)>; + }; + + soc { + flash-controller@40023c00 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(128)>; + }; + }; + }; +}; diff --git a/dts/bindings/flash_controller/st,stm32l1-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l1-flash-controller.yaml new file mode 100644 index 00000000000..75dbba2194b --- /dev/null +++ b/dts/bindings/flash_controller/st,stm32l1-flash-controller.yaml @@ -0,0 +1,15 @@ +--- +title: STM32 L1 Flash Controller +version: 0.1 + +description: > + This binding gives a base representation of the STM32 L1 Flash Controller + +inherits: + !include flash-controller.yaml + +properties: + compatible: + constraint: "st,stm32l1-flash-controller" + +... diff --git a/soc/arm/st_stm32/stm32l1/CMakeLists.txt b/soc/arm/st_stm32/stm32l1/CMakeLists.txt new file mode 100644 index 00000000000..844c5252009 --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/CMakeLists.txt @@ -0,0 +1,4 @@ +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series new file mode 100644 index 00000000000..4d4090ce408 --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series @@ -0,0 +1,15 @@ +# Kconfig - ST Microelectronics STM32L1 MCU line +# +# Copyright (c) 2019 Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_STM32L1X + +source "soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l1*" + +config SOC_SERIES + default "stm32l1" + +endif # SOC_SERIES_STM32L1X diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb new file mode 100644 index 00000000000..a823347429e --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb @@ -0,0 +1,18 @@ +# Kconfig - ST Microelectronics STM32L151XB MCU +# +# Copyright (c) 2019 Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_STM32L151XB + +config SOC + string + default "stm32l151xb" + +config NUM_IRQS + int + default 45 + +endif # SOC_STM32L151XB diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.series b/soc/arm/st_stm32/stm32l1/Kconfig.series new file mode 100644 index 00000000000..ff2f65929bc --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/Kconfig.series @@ -0,0 +1,16 @@ +# Kconfig - ST Microelectronics STM32L1 MCU series +# +# Copyright (c) 2019 Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_STM32L1X + bool "STM32L1x Series MCU" + select CPU_CORTEX_M3 + select SOC_FAMILY_STM32 + select HAS_STM32CUBE + select CPU_HAS_SYSTICK + select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL + help + Enable support for STM32L1 MCU series diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.soc b/soc/arm/st_stm32/stm32l1/Kconfig.soc new file mode 100644 index 00000000000..4a55dc5d3fd --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/Kconfig.soc @@ -0,0 +1,15 @@ +# Kconfig - ST Microelectronics STM32L1 MCU line +# +# Copyright (c) 2019 Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice +prompt "STM32L1x MCU Selection" +depends on SOC_SERIES_STM32L1X + +config SOC_STM32L151XB + bool "STM32L151XB" + +endchoice diff --git a/soc/arm/st_stm32/stm32l1/dts_fixup.h b/soc/arm/st_stm32/stm32l1/dts_fixup.h new file mode 100644 index 00000000000..c24a56ddac1 --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/dts_fixup.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2019 Linaro Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32l1/linker.ld b/soc/arm/st_stm32/stm32l1/linker.ld new file mode 100644 index 00000000000..415bbe840fb --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2019 Linaro Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/st_stm32/stm32l1/soc.c b/soc/arm/st_stm32/stm32l1/soc.c new file mode 100644 index 00000000000..543e753ab92 --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/soc.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019 Linaro Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32L1 processor + */ + +#include +#include +#include +#include +#include +#include + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int stm32l1_init(struct device *arg) +{ + u32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + z_clearfaults(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, system core clock is set to 2.1 MHz from MSI */ + SystemCoreClock = 2097000; + + return 0; +} + +SYS_INIT(stm32l1_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32l1/soc.h b/soc/arm/st_stm32/stm32l1/soc.h new file mode 100644 index 00000000000..3516986ec93 --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/soc.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019 Linaro Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32L1 family processors. + * + * Based on reference manual: + * STM32L1X advanced ARM ® -based 32-bit MCUs + * + * Chapter 2.2: Memory organization + */ + + +#ifndef _STM32L1_SOC_H_ +#define _STM32L1_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +/* ARM CMSIS definitions must be included before kernel_includes.h. + * Therefore, it is essential to include kernel_includes.h after including + * core SOC-specific headers. + */ +#include + +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32L1_SOC_H_ */ diff --git a/soc/arm/st_stm32/stm32l1/soc_registers.h b/soc/arm/st_stm32/stm32l1/soc_registers.h new file mode 100644 index 00000000000..e807cfb6df4 --- /dev/null +++ b/soc/arm/st_stm32/stm32l1/soc_registers.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019 Linaro Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _STM32L1X_SOC_REGISTERS_H_ +#define _STM32L1X_SOC_REGISTERS_H_ + +/* include register mapping headers */ + +#endif /* _STM32L1X_SOC_REGISTERS_H_ */