michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers/clock_control: stm32: style edits on set_up_fixed_clock_sources()

Browse source 
Review code style in set_up_fixed_clock_sources() for better
readability.
Use of 'if (IS_ENABLED(STM32_MSI_ENABLED))' inside '#if STM32_MSI_ENABLED'
is redundant but intentional as it is in line with remaining part of the
function (HSE/HSI cases).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-25 12:05:08 +01:00 • committed by Carles Cufí
commit 92a741c2ae
1 changed files with 43 additions and 41 deletions
Download patch file Download diff file Expand all files Collapse all files

22
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -386,12 +386,8 @@ static int set_up_plls(void)
static void set_up_fixed_clock_sources(void) static void set_up_fixed_clock_sources(void)
{ {
#if STM32_HSE_ENABLED if (IS_ENABLED(STM32_HSE_ENABLED)) {
#ifdef CONFIG_SOC_SERIES_STM32WLX #if defined(STM32_HSE_BYPASS)
if (IS_ENABLED(STM32_HSE_TCXO)) {
LL_RCC_HSE_EnableTcxo();
}
#elif !defined(CONFIG_SOC_SERIES_STM32WBX)
/* Check if need to enable HSE bypass feature or not */ /* Check if need to enable HSE bypass feature or not */
if (IS_ENABLED(STM32_HSE_BYPASS)) { if (IS_ENABLED(STM32_HSE_BYPASS)) {
LL_RCC_HSE_EnableBypass(); LL_RCC_HSE_EnableBypass();
@ -399,6 +395,9 @@ static void set_up_fixed_clock_sources(void)
LL_RCC_HSE_DisableBypass(); LL_RCC_HSE_DisableBypass();
} }
#endif #endif
#if STM32_HSE_TCXO
LL_RCC_HSE_EnableTcxo();
#endif
#if STM32_HSE_DIV2 #if STM32_HSE_DIV2
LL_RCC_HSE_EnableDiv2(); LL_RCC_HSE_EnableDiv2();
#endif #endif
@ -407,9 +406,9 @@ static void set_up_fixed_clock_sources(void)
while (LL_RCC_HSE_IsReady() != 1) { while (LL_RCC_HSE_IsReady() != 1) {
/* Wait for HSE ready */ /* Wait for HSE ready */
} }
#endif /* STM32_HSE_ENABLED */ }
#if STM32_HSI_ENABLED if (IS_ENABLED(STM32_HSI_ENABLED)) {
/* Enable HSI if not enabled */ /* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1) { if (LL_RCC_HSI_IsReady() != 1) {
/* Enable HSI */ /* Enable HSI */
@ -418,9 +417,10 @@ static void set_up_fixed_clock_sources(void)
/* Wait for HSI ready */ /* Wait for HSI ready */
} }
} }
#endif /* STM32_HSI_ENABLED */ }
#if STM32_MSI_ENABLED #if defined(STM32_MSI_ENABLED)
if (IS_ENABLED(STM32_MSI_ENABLED)) {
/* Set MSI Range */ /* Set MSI Range */
#if defined(RCC_CR_MSIRGSEL) #if defined(RCC_CR_MSIRGSEL)
LL_RCC_MSI_EnableRangeSelection(); LL_RCC_MSI_EnableRangeSelection();
@ -436,6 +436,7 @@ static void set_up_fixed_clock_sources(void)
/* Enable MSI hardware auto calibration */ /* Enable MSI hardware auto calibration */
LL_RCC_MSI_EnablePLLMode(); LL_RCC_MSI_EnablePLLMode();
#endif #endif
LL_RCC_MSI_SetCalibTrimming(0); LL_RCC_MSI_SetCalibTrimming(0);
/* Enable MSI if not enabled */ /* Enable MSI if not enabled */
@ -446,6 +447,7 @@ static void set_up_fixed_clock_sources(void)
/* Wait for MSI ready */ /* Wait for MSI ready */
} }
} }
}
#endif /* STM32_MSI_ENABLED */ #endif /* STM32_MSI_ENABLED */
} }