drivers: Extend Atmel SAM GPIO driver
Add soc_gpio_get(), soc_gpio_debounce_length_set() functions to Atmel SAM soc_gpio driver. Change-Id: I541c6fead9a308dd2e67c59dabe67b87cf1628ef Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
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1 changed files with 44 additions and 5 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016 Piotr Mienkowski
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* Copyright (c) 2016-2017 Piotr Mienkowski
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -112,13 +112,13 @@ void soc_gpio_list_configure(const struct soc_gpio_pin pins[],
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unsigned int size);
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/**
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* \brief Set pin(s) high.
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* @brief Set pin(s) high.
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*
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* Set pin(s) defined in the mask parameter to high. The pin(s) have to be
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* configured as output by the configure function. The flags field which
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* is part of pin struct is ignored.
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*
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* \param pin pointer to a pin instance describing one or more pins.
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* @param pin pointer to a pin instance describing one or more pins.
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*/
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static inline void soc_gpio_set(const struct soc_gpio_pin *pin)
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{
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@ -126,17 +126,56 @@ static inline void soc_gpio_set(const struct soc_gpio_pin *pin)
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}
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/**
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* \brief Set pin(s) low.
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* @brief Set pin(s) low.
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*
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* Set pin(s) defined in the mask field to low. The pin(s) have to be
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* configured as output by the configure function. The flags field which
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* is part of pin struct is ignored.
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*
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* \param pin pointer to a pin instance describing one or more pins.
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* @param pin pointer to a pin instance describing one or more pins.
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*/
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static inline void soc_gpio_clear(const struct soc_gpio_pin *pin)
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{
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pin->regs->PIO_CODR = pin->mask;
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}
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/**
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* @brief Get pin(s) value.
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*
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* Get value of the pin(s) defined in the mask field.
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*
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* @param pin pointer to a pin instance describing one or more pins.
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* @return pin(s) value. To assess value of a specific pin the pin's bit
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* field has to be read.
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*/
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static inline uint32_t soc_gpio_get(const struct soc_gpio_pin *pin)
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{
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return pin->regs->PIO_PDSR & pin->mask;
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}
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/**
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* @brief Set the length of the debounce window.
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*
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* The debouncing filter automatically rejects a pulse with a duration of less
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* than 1/2 programmable divided slow clock period tdiv_slck, while a pulse with
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* a duration of one or more tdiv_slck cycles is accepted. For pulse durations
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* between 1/2 selected clock cycle and one tdiv_slck clock cycle, the pulse may
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* or may not be taken into account, depending on the precise timing of its
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* occurrence.
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*
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* tdiv_slck = ((div + 1) × 2) × tslck
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* where tslck is the slow clock, typically 32.768 kHz.
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*
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* Setting the length of the debounce window is only meaningful if the pin is
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* configured as input and the debounce pin option is enabled.
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*
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* @param pin pointer to a pin instance describing one or more pins.
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* @param div slow clock divider, valid values: from 0 to 2^14 - 1
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*/
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static inline void soc_gpio_debounce_length_set(const struct soc_gpio_pin *pin,
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uint32_t div)
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{
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pin->regs->PIO_SCDR = PIO_SCDR_DIV(div);
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}
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#endif /* _ATMEL_SAM_SOC_GPIO_H_ */
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