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soc: esp32c6: Kconfig and .ld updates, DTS and comments fix

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Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit is contained in:
Raffael Rostagno 2024-05-29 17:58:15 -03:00 • committed by Anas Nashif
commit 9265c82313
8 changed files with 26 additions and 31 deletions
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2
arch/Kconfig
View file

@ -110,7 +110,7 @@ config RISCV
bool
select ARCH_IS_SET
select ARCH_SUPPORTS_COREDUMP
select ARCH_SUPPORTS_ROM_START if !SOC_SERIES_ESP32C3
select ARCH_SUPPORTS_ROM_START if !SOC_FAMILY_ESPRESSIF_ESP32
select ARCH_HAS_CODE_DATA_RELOCATION
select ARCH_HAS_THREAD_LOCAL_STORAGE
select ARCH_HAS_STACKWALK

18
dts/riscv/espressif/esp32c6/esp32c6_common.dtsi
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,7 +25,7 @@
cpu0: cpu@0 {
device_type = "cpu";
compatible = "espressif,riscv";
riscv,isa = "rv32imc_zicsr";
riscv,isa = "rv32imac_zicsr";
reg = <0>;
clock-source = <ESP32_CPU_CLK_SRC_PLL>;
clock-frequency = <DT_FREQ_M(160)>;
@ -82,7 +82,7 @@
clocks = <&rtc ESP32_MODULE_MAX>;
interrupts = <LP_RTC_TIMER_INTR_SOURCE>;
interrupt-parent = <&intc>;
status = "okay";
status = "disabled";
};
spi2: spi@60081000 {
@ -96,18 +96,18 @@
status = "disabled";
};
wdt0: watchdog@6001f048 {
wdt0: watchdog@60008048 {
compatible = "espressif,esp32-watchdog";
reg = <0x6001f048 0x20>;
reg = <0x60008048 0x20>;
interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG0_MODULE>;
status = "disabled";
};
wdt1: watchdog@60020048 {
wdt1: watchdog@60009048 {
compatible = "espressif,esp32-watchdog";
reg = <0x60020048 0x20>;
reg = <0x60009048 0x20>;
interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG1_MODULE>;
@ -147,9 +147,9 @@
clocks = <&rtc ESP32_UART0_MODULE>;
};
uart1: uart@60010000 {
uart1: uart@60001000 {
compatible = "espressif,esp32-uart";
reg = <0x60010000 DT_SIZE_K(4)>;
reg = <0x60001000 DT_SIZE_K(4)>;
status = "disabled";
interrupts = <UART1_INTR_SOURCE>;
interrupt-parent = <&intc>;

8
soc/espressif/esp32c6/Kconfig
View file

@ -1,4 +1,4 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_ESP32C6
@ -8,6 +8,7 @@ config SOC_SERIES_ESP32C6
select CLOCK_CONTROL
select PINCTRL
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
@ -18,10 +19,6 @@ config SOC_SERIES_ESP32C6
if SOC_SERIES_ESP32C6
config IDF_TARGET_ESP32C6
bool "ESP32C6 as target board"
default y
config ESP32_PHY_MAX_WIFI_TX_POWER
int "Max WiFi TX power (dBm)"
range 10 20
@ -37,7 +34,6 @@ config ESP32_PHY_MAX_TX_POWER
config MAC_BB_PD
bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
depends on SOC_SERIES_ESP32C6 && TICKLESS_KERNEL
default n
help
If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
down when PHY is disabled. Enabling this setting reduces power consumption

4
soc/espressif/esp32c6/Kconfig.defconfig
View file

@ -1,6 +1,6 @@
# ESP32C3 board configuration
# ESP32C6 board configuration
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C6

5
soc/espressif/esp32c6/Kconfig.soc
View file

@ -1,4 +1,4 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_ESP32C6
@ -21,9 +21,8 @@ config SOC_SERIES
default "esp32c6" if SOC_SERIES_ESP32C6
config SOC
default "esp32c6" if SOC_SERIES_ESP32C6
default "esp32c6" if SOC_ESP32C6
config SOC_PART_NUMBER
default "ESP32_C6_WROOM_1U_N4" if SOC_ESP32_C6_WROOM_1U_N4
default "ESP32_C6_WROOM_1U_N8" if SOC_ESP32_C6_WROOM_1U_N8
default "ESP32C6" if SOC_ESP32C6

16
soc/espressif/esp32c6/default.ld
View file

@ -610,8 +610,6 @@ SECTIONS
__bss_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
/* bluetooth library requires this symbol to be defined */
_btdm_bss_start = ABSOLUTE(.);
*libbtdm_app.a:(.bss .bss.* COMMON)
. = ALIGN (4);
_btdm_bss_end = ABSOLUTE(.);
@ -662,6 +660,7 @@ SECTIONS
_instruction_reserved_start = ABSOLUTE(.);
_text_start = ABSOLUTE(.);
_instruction_reserved_start = ABSOLUTE(.);
__text_region_start = ABSOLUTE(.);
#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
@ -692,6 +691,7 @@ SECTIONS
_instruction_reserved_end = ABSOLUTE(.);
_text_end = ABSOLUTE(.);
_instruction_reserved_end = ABSOLUTE(.);
__text_region_end = ABSOLUTE(.);
_etext = .;
} GROUP_DATA_LINK_IN(CACHED_REGION, ROMABLE_REGION)
@ -701,17 +701,17 @@ SECTIONS
/* --- START OF .rodata --- */
/* Align next section to 64k to allow mapping */
.flash.align_rodata (NOLOAD) :
{
/* Subsequent segment lma and vma align */
. = ALIGN(CACHE_ALIGN);
} GROUP_DATA_LINK_IN(CACHED_REGION, ROMABLE_REGION)
.flash.align_rom (NOLOAD) :
{
. = ALIGN(CACHE_ALIGN);
} GROUP_LINK_IN(ROMABLE_REGION)
.flash.align_rodata (NOLOAD) :
{
/* Subsequent segment lma and vma align */
. = ALIGN(CACHE_ALIGN);
} GROUP_LINK_IN(CACHED_REGION)
/* Symbols used during the application memory mapping */
_image_drom_start = LOADADDR(.flash.rodata);
_image_drom_size = _image_rodata_end - _image_rodata_start;

2
soc/espressif/esp32c6/mcuboot.ld
View file

@ -101,7 +101,7 @@ SECTIONS
*(.iram1 .iram1.*)
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
/* C3 memprot requires 512 B alignment for split lines */
/* C6 memprot requires 512 B alignment for split lines */
. = ALIGN (16);
_init_end = ABSOLUTE(.);
. = ALIGN(16);