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ext: hal: nordic: Update nrfx to version 1.6.2

Browse source 
Updates nrfx to the recently released version. See
https://github.com/NordicSemiconductor/nrfx/blob/v1.6.2/CHANGELOG.md
for a list of changes that this version introduces.

Origin: nrfx
License: BSD 3-Clause
URL: https://github.com/NordicSemiconductor/nrfx/tree/v1.6.2
commit: 6f54f689e9555ea18f9aca87caf44a3419e5dd7a
Purpose: Provide peripheral drivers for Nordic SoCs
Maintained-by: External

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2019-02-07 08:12:50 +01:00 • committed by Kumar Gala
commit 91bd31e883
148 changed files with 133642 additions and 67347 deletions
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8
ext/hal/nordic/nrfx/README
View file

@ -2,10 +2,10 @@ nrfx
####
Origin:
https://github.com/NordicSemiconductor/nrfx/tree/v1.5.0
https://github.com/NordicSemiconductor/nrfx/tree/v1.6.2
Status:
v1.5.0
v1.6.2
Purpose:
With added proper shims adapting it to Zephyr's APIs, nrfx will provide
@ -32,7 +32,7 @@ URL:
https://github.com/NordicSemiconductor/nrfx
commit:
2f4572bd2ae640a6140959f39de282e9f58c739c
6f54f689e9555ea18f9aca87caf44a3419e5dd7a
Maintained-by:
External
@ -41,4 +41,4 @@ License:
BSD-3-Clause
License Link:
https://github.com/NordicSemiconductor/nrfx/blob/v1.5.0/LICENSE
https://github.com/NordicSemiconductor/nrfx/blob/v1.6.2/LICENSE

2
ext/hal/nordic/nrfx/drivers/include/nrf_bitmask.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_adc.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_clock.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_comp.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_dppi.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_gpiote.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_i2s.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_lpcomp.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_nfct.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_pdm.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_power.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_power_clock.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_ppi.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_pwm.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_qdec.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_qspi.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_rng.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_rtc.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_saadc.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_spi.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_spim.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_spis.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_swi.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_systick.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_timer.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_twi.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_twim.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_twis.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_uart.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_uarte.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_usbd.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/include/nrfx_wdt.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

26
ext/hal/nordic/nrfx/drivers/nrfx_common.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -173,22 +173,32 @@ do { \
} while (--remaining_attempts); \
} while(0)
/**
* @brief Macro for getting the ID number of the specified peripheral.
*
* For peripherals in Nordic SoCs, there is a direct relationship between their
* ID numbers and their base addresses. See the chapter "Peripheral interface"
* (section "Peripheral ID") in the Product Specification.
*
* @param[in] base_addr Peripheral base address or pointer.
*
* @return ID number associated with the specified peripheral.
*/
#define NRFX_PERIPHERAL_ID_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12)
/**
* @brief Macro for getting the interrupt number assigned to a specific
* peripheral.
*
* In Nordic SoCs the IRQ number assigned to a peripheral is equal to the ID
* of this peripheral, and there is a direct relationship between this ID and
* the peripheral base address, i.e. the address of a fixed block of 0x1000
* bytes of address space assigned to this peripheral.
* See the chapter "Peripheral interface" (sections "Peripheral ID" and
* "Interrupts") in the product specification of a given SoC.
* For peripherals in Nordic SoCs, the IRQ number assigned to a peripheral is
* equal to its ID number. See the chapter "Peripheral interface" (sections
* "Peripheral ID" and "Interrupts") in the Product Specification.
*
* @param[in] base_addr Peripheral base address or pointer.
*
* @return Interrupt number associated with the specified peripheral.
*/
#define NRFX_IRQ_NUMBER_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12)
#define NRFX_IRQ_NUMBER_GET(base_addr) NRFX_PERIPHERAL_ID_GET(base_addr)
/**
* @brief IRQ handler type.

2
ext/hal/nordic/nrfx/drivers/nrfx_errors.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_adc.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_clock.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

8
ext/hal/nordic/nrfx/drivers/src/nrfx_comp.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -133,8 +133,8 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config,
nrf_comp_input_select(p_config->input);
NRFX_IRQ_PRIORITY_SET(COMP_LPCOMP_IRQn, p_config->interrupt_priority);
NRFX_IRQ_ENABLE(COMP_LPCOMP_IRQn);
NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_COMP), p_config->interrupt_priority);
NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_COMP));
m_state = NRFX_DRV_STATE_INITIALIZED;
@ -146,7 +146,7 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config,
void nrfx_comp_uninit(void)
{
NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED);
NRFX_IRQ_DISABLE(COMP_LPCOMP_IRQn);
NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_COMP));
nrf_comp_disable();
#if NRFX_CHECK(NRFX_PRS_ENABLED)
nrfx_prs_release(NRF_COMP);

2
ext/hal/nordic/nrfx/drivers/src/nrfx_dppi.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_gpiote.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

22
ext/hal/nordic/nrfx/drivers/src/nrfx_i2s.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -45,14 +45,12 @@
(event == NRF_I2S_EVENT_STOPPED ? "NRF_I2S_EVENT_STOPPED" : \
"UNKNOWN EVENT")))
#if !defined(USE_WORKAROUND_FOR_ANOMALY_194) && \
(defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
defined(NRF52840_XXAA))
// Enable workaround for nRF52832 and nRF52840 anomaly 194 (STOP task does not
// switch off all resources).
#define USE_WORKAROUND_FOR_ANOMALY_194 1
#else
#define USE_WORKAROUND_FOR_ANOMALY_194 0
#if !defined(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY) && \
(defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA) || \
defined(NRF9160_XXAA))
// Enable workaround for nRF52832 and nRF52840 anomaly 194 / nrf9160 anomaly 1
// (STOP task does not switch off all resources).
#define USE_WORKAROUND_FOR_I2S_STOP_ANOMALY 1
#endif
// Control block - driver instance local data.
@ -344,9 +342,9 @@ void nrfx_i2s_stop(void)
NRF_I2S_INT_TXPTRUPD_MASK);
nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_STOP);
#if USE_WORKAROUND_FOR_ANOMALY_194
*((volatile uint32_t *)0x40025038) = 1;
*((volatile uint32_t *)0x4002503C) = 1;
#if NRFX_CHECK(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY)
*((volatile uint32_t *)(((uint32_t)NRF_I2S) + 0x38)) = 1;
*((volatile uint32_t *)(((uint32_t)NRF_I2S) + 0x3C)) = 1;
#endif
}

2
ext/hal/nordic/nrfx/drivers/src/nrfx_lpcomp.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

5
ext/hal/nordic/nrfx/drivers/src/nrfx_nfct.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -346,6 +346,9 @@ static inline void nrfx_nfct_reset(void)
// Restore interrupts.
nrf_nfct_int_enable(int_enabled);
// Disable interrupts associated with data exchange.
nrf_nfct_int_disable(NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
NRFX_LOG_INFO("Reinitialize");
}

2
ext/hal/nordic/nrfx/drivers/src/nrfx_pdm.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_power.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_ppi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_pwm.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_qdec.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_qspi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_rng.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_rtc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

5
ext/hal/nordic/nrfx/drivers/src/nrfx_saadc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -228,6 +228,7 @@ nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config,
nrf_saadc_int_disable(NRF_SAADC_INT_ALL);
nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED);
nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED);
NRFX_IRQ_PRIORITY_SET(SAADC_IRQn, p_config->interrupt_priority);
NRFX_IRQ_ENABLE(SAADC_IRQn);
nrf_saadc_int_enable(NRF_SAADC_INT_END);
@ -580,7 +581,7 @@ void nrfx_saadc_abort(void)
{
// Wait for ADC being stopped.
bool result;
NRFX_WAIT_FOR((m_cb.adc_state != NRF_SAADC_STATE_IDLE), HW_TIMEOUT, 0, result);
NRFX_WAIT_FOR((m_cb.adc_state == NRF_SAADC_STATE_IDLE), HW_TIMEOUT, 0, result);
NRFX_ASSERT(result);
}

2
ext/hal/nordic/nrfx/drivers/src/nrfx_spi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_spim.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_spis.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2013 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

10
ext/hal/nordic/nrfx/drivers/src/nrfx_swi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -155,10 +155,12 @@ static bool swi_is_available(nrfx_swi_t swi)
static IRQn_Type swi_irq_number_get(nrfx_swi_t swi)
{
#if defined(SWI_PRESENT)
return (IRQn_Type)((uint32_t)SWI0_IRQn + (uint32_t)swi);
#if defined(NRF_SWI)
return (IRQn_Type)(nrfx_get_irq_number(NRF_SWI) + swi);
#elif defined(NRF_SWI0)
return (IRQn_Type)(nrfx_get_irq_number(NRF_SWI0) + swi);
#else
return (IRQn_Type)((uint32_t)EGU0_IRQn + (uint32_t)swi);
return (IRQn_Type)(nrfx_get_irq_number(NRF_EGU0) + swi);
#endif
}

2
ext/hal/nordic/nrfx/drivers/src/nrfx_systick.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_timer.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

6
ext/hal/nordic/nrfx/drivers/src/nrfx_twi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -209,8 +209,8 @@ void nrfx_twi_uninit(nrfx_twi_t const * p_instance)
if (!p_cb->hold_bus_uninit)
{
nrf_gpio_cfg_default(p_instance->p_twi->PSELSCL);
nrf_gpio_cfg_default(p_instance->p_twi->PSELSDA);
nrf_gpio_cfg_default(nrf_twi_scl_pin_get(p_instance->p_twi));
nrf_gpio_cfg_default(nrf_twi_sda_pin_get(p_instance->p_twi));
}
p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;

2
ext/hal/nordic/nrfx/drivers/src/nrfx_twim.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_twis.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/nrfx_uart.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
ext/hal/nordic/nrfx/drivers/src/nrfx_uarte.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -93,7 +93,7 @@ typedef struct
uint8_t const * p_tx_buffer;
uint8_t * p_rx_buffer;
uint8_t * p_rx_secondary_buffer;
size_t tx_buffer_length;
volatile size_t tx_buffer_length;
size_t rx_buffer_length;
size_t rx_secondary_buffer_length;
nrfx_drv_state_t state;

35
ext/hal/nordic/nrfx/drivers/src/nrfx_usbd.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -65,6 +65,10 @@
#endif
#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
/*
* Respond to an IN token on ISO IN endpoint with ZLP when no data is ready.
* NOTE: This option does not work on Engineering A chip.
*/
#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
#endif
@ -265,7 +269,7 @@ static uint32_t m_ep_ready;
* Mask prepared USBD data for transmission.
* It is cleared when no more data to transmit left.
*/
static atomic_t m_ep_dma_waiting;
static uint32_t m_ep_dma_waiting;
/**
* @brief Current EasyDMA state.
@ -753,13 +757,11 @@ static inline void usbd_dma_start(nrfx_usbd_ep_t ep)
void nrfx_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config)
{
NRFX_ASSERT(!nrfx_usbd_errata_type_52840_eng_a());
nrf_usbd_isoinconfig_set(config);
}
nrf_usbd_isoinconfig_t nrfx_usbd_isoinconfig_get(void)
{
NRFX_ASSERT(!nrfx_usbd_errata_type_52840_eng_a());
return nrf_usbd_isoinconfig_get();
}
@ -850,7 +852,7 @@ void nrfx_usbd_ep_abort(nrfx_usbd_ep_t ep)
*/
static void usbd_ep_abort_all(void)
{
atomic_t ep_waiting = m_ep_dma_waiting | (m_ep_ready & NRFX_USBD_EPOUT_BIT_MASK);
uint32_t ep_waiting = m_ep_dma_waiting | (m_ep_ready & NRFX_USBD_EPOUT_BIT_MASK);
while (0 != ep_waiting)
{
uint8_t bitpos = __CLZ(__RBIT(ep_waiting));
@ -1657,12 +1659,6 @@ void nrfx_usbd_irq_handler(void)
nrfx_err_t nrfx_usbd_init(nrfx_usbd_event_handler_t event_handler)
{
NRFX_ASSERT((nrfx_usbd_errata_type_52840_eng_a() ||
nrfx_usbd_errata_type_52840_eng_b() ||
nrfx_usbd_errata_type_52840_eng_c() ||
nrfx_usbd_errata_type_52840_eng_d())
);
NRFX_ASSERT(event_handler);
if (m_drv_state != NRFX_DRV_STATE_UNINITIALIZED)
@ -1864,6 +1860,9 @@ void nrfx_usbd_stop(void)
{
NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_POWERED_ON);
/* Clear interrupt */
NRFX_IRQ_PENDING_CLEAR(USBD_IRQn);
if (NRFX_IRQ_IS_ENABLED(USBD_IRQn))
{
/* Abort transfers */
@ -1914,20 +1913,6 @@ bool nrfx_usbd_suspend(void)
else
{
suspended = true;
if (nrfx_usbd_errata_171())
{
if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
{
*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
*((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
}
else
{
*((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
}
}
}
}
}

22
ext/hal/nordic/nrfx/drivers/src/nrfx_usbd_errata.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -50,34 +50,34 @@ static inline bool nrfx_usbd_errata_type_52840(void)
static inline bool nrfx_usbd_errata_type_52840_eng_a(void)
{
return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x0UL));
return nrfx_usbd_errata_type_52840();
}
static inline bool nrfx_usbd_errata_type_52840_eng_b(void)
{
return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x1UL));
return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x1UL));
}
static inline bool nrfx_usbd_errata_type_52840_eng_c(void)
{
return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x2UL));
return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x2UL));
}
static inline bool nrfx_usbd_errata_type_52840_eng_d(void)
{
return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x3UL));
return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x3UL));
}
/* Errata: USBD: EPDATA event is not always generated. */
static inline bool nrfx_usbd_errata_104(void)
{
return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a());
return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b()));
}
/* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task. */
static inline bool nrfx_usbd_errata_154(void)
{
return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a());
return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b()));
}
/* Errata: ISO double buffering not functional. */
@ -95,11 +95,7 @@ static inline bool nrfx_usbd_errata_171(void)
/* Errata: USB cannot be enabled. */
static inline bool nrfx_usbd_errata_187(void)
{
return (NRFX_USBD_ERRATA_ENABLE &&
(nrfx_usbd_errata_type_52840_eng_b() ||
nrfx_usbd_errata_type_52840_eng_c() ||
nrfx_usbd_errata_type_52840_eng_d())
);
return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_b());
}
/* Errata: USBD cannot receive tasks during DMA. */
@ -111,7 +107,7 @@ static inline bool nrfx_usbd_errata_199(void)
/* Errata: SIZE.EPOUT not writable. */
static inline bool nrfx_usbd_errata_200(void)
{
return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a());
return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b()));
}
#endif // NRFX_USBD_ERRATA_H__

2
ext/hal/nordic/nrfx/drivers/src/nrfx_wdt.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/drivers/src/prs/nrfx_prs.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

15
ext/hal/nordic/nrfx/drivers/src/prs/nrfx_prs.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -52,10 +52,19 @@ extern "C" {
// SPI1, SPIS1, TWI1
#define NRFX_PRS_BOX_1_ADDR NRF_SPI1
#elif defined(NRF52810_XXAA)
// TWIM0, TWIS0
// TWIM0, TWIS0, TWI0
#define NRFX_PRS_BOX_0_ADDR NRF_TWIM0
// SPIM0, SPIS0
// SPIM0, SPIS0, SPI0
#define NRFX_PRS_BOX_1_ADDR NRF_SPIM0
// UARTE0, UART0
#define NRFX_PRS_BOX_2_ADDR NRF_UARTE0
#elif defined(NRF52811_XXAA)
// TWIM0, TWIS0, TWI0, SPIM1, SPIS1, SPI1
#define NRFX_PRS_BOX_0_ADDR NRF_TWIM0
// SPIM0, SPIS0, SPI0
#define NRFX_PRS_BOX_1_ADDR NRF_SPIM0
// UART0, UARTE0
#define NRFX_PRS_BOX_2_ADDR NRF_UART0
#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
// SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0
#define NRFX_PRS_BOX_0_ADDR NRF_SPIM0

2
ext/hal/nordic/nrfx/hal/nrf_acl.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_adc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

125
ext/hal/nordic/nrfx/hal/nrf_bprot.h Normal file
View file

@ -0,0 +1,125 @@
/*
* Copyright (c) 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF_BPROT_H__
#define NRF_BPROT_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_bprot_hal BPROT HAL
* @{
* @ingroup nrf_bprot
* @brief Hardware access layer for managing the Block Protection (BPROT) mechanism.
*/
/**
* @brief Function for enabling protection for specified non-volatile memory blocks.
*
* Blocks are arranged into groups of 32 blocks each. Each block size is 4 kB.
* Any attempt to write or erase a protected block will result in hard fault.
* The memory block protection can be disabled only by resetting the device.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] group_idx Non-volatile memory group containing memory blocks to protect.
* @param[in] block_mask Non-volatile memory blocks to protect. Each bit in bitmask represents
* one memory block in the specified group.
*/
__STATIC_INLINE void nrf_bprot_nvm_blocks_protection_enable(NRF_BPROT_Type * p_reg,
uint8_t group_idx,
uint32_t block_mask);
/**
* @brief Function for setting the non-volatile memory (NVM) protection during debug.
*
* NVM protection is disabled by default while debugging.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] enable True if NVM protection during debug is to be enabled.
* False if otherwise.
*/
__STATIC_INLINE void nrf_bprot_nvm_protection_in_debug_set(NRF_BPROT_Type * p_reg,
bool enable);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_bprot_nvm_blocks_protection_enable(NRF_BPROT_Type * p_reg,
uint8_t group_idx,
uint32_t block_mask)
{
switch (group_idx)
{
case 0:
p_reg->CONFIG0 = block_mask;
break;
case 1:
p_reg->CONFIG1 = block_mask;
break;
#if defined(BPROT_CONFIG2_REGION64_Pos)
case 2:
p_reg->CONFIG2 = block_mask;
break;
#endif
#if defined(BPROT_CONFIG3_REGION96_Pos)
case 3:
p_reg->CONFIG3 = block_mask;
break;
#endif
default:
NRFX_ASSERT(false);
break;
}
}
__STATIC_INLINE void nrf_bprot_nvm_protection_in_debug_set(NRF_BPROT_Type * p_reg,
bool enable)
{
p_reg->DISABLEINDEBUG =
(enable ? 0 : BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_BPROT_H__

2
ext/hal/nordic/nrfx/hal/nrf_ccm.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_clock.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_comp.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_dppi.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_ecb.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2012 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_ecb.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2012 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_egu.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

18
ext/hal/nordic/nrfx/hal/nrf_gpio.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -325,6 +325,15 @@ __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
*/
__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
/**
* @brief Function for reading the status of GPIO pin input buffer.
*
* @param pin_number Pin number to be read.
*
* @retval Input buffer configuration.
*/
__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number);
/**
* @brief Function for reading the pull configuration of a GPIO pin.
*
@ -694,6 +703,13 @@ __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
}
__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number)
{
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] &
GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos);
}
__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
{

2
ext/hal/nordic/nrfx/hal/nrf_gpiote.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_i2s.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_kmu.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_lpcomp.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

176
ext/hal/nordic/nrfx/hal/nrf_mpu.h Normal file
View file

@ -0,0 +1,176 @@
/*
* Copyright (c) 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF_MPU_H__
#define NRF_MPU_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_mpu_hal MPU HAL
* @{
* @ingroup nrf_mpu
* @brief Hardware access layer for managing the Memory Protection Unit (MPU) peripheral.
*/
/**
* @brief Macro for getting MPU region configuration mask for the specified peripheral.
*
* @param[in] base_addr Peripheral base address.
*
* @return MPU configuration mask for the specified peripheral.
*/
#define NRF_MPU_PERIPHERAL_MASK_GET(base_addr) (1UL << NRFX_PERIPHERAL_ID_GET(base_addr))
/**
* @brief Function for setting the size of the RAM region 0.
*
* When memory protection is enabled, the Memory Protection Unit enforces
* runtime protection and readback protection of resources classified as region 0.
* See the product specification for more information.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] size Size of the RAM region 0, in bytes. Must be word-aligned.
*/
__STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size);
/**
* @brief Function for configuring specified peripherals in the memory region 0.
*
* When the memory protection is enabled, the Memory Protection Unit enforces
* runtime protection and readback protection of resources classified as region 0.
* See the product specification for more information.
*
* After reset, all peripherals are configured as *not* assigned to region 0.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] peripheral_mask Mask that specifies peripherals to be configured in the memory region 0.
* Compose this mask using @ref NRF_MPU_PERIPHERAL_MASK_GET macro.
*/
__STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
uint32_t peripheral_mask);
/**
* @brief Function for getting the bitmask that specifies peripherals configured in the memory region 0.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Bitmask representing peripherals configured in region 0.
*/
__STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg);
/**
* @brief Function for enabling protection for specified non-volatile memory blocks.
*
* Blocks are arranged into groups of 32 blocks each. Each block size is 4 kB.
* Any attempt to write or erase a protected block will result in hard fault.
* The memory block protection can be disabled only by resetting the device.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] group_idx Non-volatile memory group containing memory blocks to protect.
* @param[in] block_mask Non-volatile memory blocks to protect. Each bit in bitmask represents
* one memory block in the specified group.
*/
__STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
uint8_t group_idx,
uint32_t block_mask);
/**
* @brief Function for setting the non-volatile memory (NVM) protection during debug.
*
* NVM protection during debug is disabled by default.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] enable True if NVM protection during debug is to be enabled.
* False if otherwise.
*/
__STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
bool enable);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size)
{
NRFX_ASSERT(nrfx_is_word_aligned((const void *)size));
p_reg->RLENR0 = size;
}
__STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
uint32_t peripheral_mask)
{
p_reg->PERR0 = peripheral_mask;
}
__STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg)
{
return p_reg->PERR0;
}
__STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
uint8_t group_idx,
uint32_t block_mask)
{
switch (group_idx)
{
case 0:
p_reg->PROTENSET0 = block_mask;
break;
case 1:
p_reg->PROTENSET1 = block_mask;
break;
default:
NRFX_ASSERT(false);
break;
}
}
__STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
bool enable)
{
p_reg->DISABLEINDEBUG =
(enable ? 0 : MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_MPU_H__

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/*
* Copyright (c) 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRF_MWU_H__
#define NRF_MWU_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_mwu_hal MWU HAL
* @{
* @ingroup nrf_mwu
* @brief Hardware access layer for managing the Memory Watch Unit (MWU) peripheral.
*/
/** @brief MWU events. */
typedef enum
{
NRF_MWU_EVENT_REGION0_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[0].WA), ///< Write access to region 0 detected.
NRF_MWU_EVENT_REGION0_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[0].RA), ///< Read access to region 0 detected.
NRF_MWU_EVENT_REGION1_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[1].WA), ///< Write access to region 1 detected.
NRF_MWU_EVENT_REGION1_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[1].RA), ///< Read access to region 1 detected.
NRF_MWU_EVENT_REGION2_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[2].WA), ///< Write access to region 2 detected.
NRF_MWU_EVENT_REGION2_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[2].RA), ///< Read access to region 2 detected.
NRF_MWU_EVENT_REGION3_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[3].WA), ///< Write access to region 3 detected.
NRF_MWU_EVENT_REGION3_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[3].RA), ///< Read access to region 3 detected.
NRF_MWU_EVENT_PREGION0_WRITE = offsetof(NRF_MWU_Type, EVENTS_PREGION[0].WA), ///< Write access to peripheral region 0 detected.
NRF_MWU_EVENT_PREGION0_READ = offsetof(NRF_MWU_Type, EVENTS_PREGION[0].RA), ///< Read access to peripheral region 0 detected.
NRF_MWU_EVENT_PREGION1_WRITE = offsetof(NRF_MWU_Type, EVENTS_PREGION[1].WA), ///< Write access to peripheral region 1 detected.
NRF_MWU_EVENT_PREGION1_READ = offsetof(NRF_MWU_Type, EVENTS_PREGION[1].RA), ///< Read access to peripheral region 1 detected.
} nrf_mwu_event_t;
/** @brief MWU interrupt masks. */
typedef enum
{
NRF_MWU_INT_REGION0_WRITE_MASK = MWU_INTEN_REGION0WA_Msk, ///< Interrupt on REGION[0].WA event.
NRF_MWU_INT_REGION0_READ_MASK = MWU_INTEN_REGION0RA_Msk, ///< Interrupt on REGION[0].RA event.
NRF_MWU_INT_REGION1_WRITE_MASK = MWU_INTEN_REGION1WA_Msk, ///< Interrupt on REGION[1].WA event.
NRF_MWU_INT_REGION1_READ_MASK = MWU_INTEN_REGION1RA_Msk, ///< Interrupt on REGION[1].RA event.
NRF_MWU_INT_REGION2_WRITE_MASK = MWU_INTEN_REGION2WA_Msk, ///< Interrupt on REGION[2].WA event.
NRF_MWU_INT_REGION2_READ_MASK = MWU_INTEN_REGION2RA_Msk, ///< Interrupt on REGION[2].RA event.
NRF_MWU_INT_REGION3_WRITE_MASK = MWU_INTEN_REGION3WA_Msk, ///< Interrupt on REGION[3].WA event.
NRF_MWU_INT_REGION3_READ_MASK = MWU_INTEN_REGION3RA_Msk, ///< Interrupt on REGION[3].RA event.
NRF_MWU_INT_PREGION0_WRITE_MASK = MWU_INTEN_PREGION0WA_Msk, ///< Interrupt on PREGION[0].WA event.
NRF_MWU_INT_PREGION0_READ_MASK = MWU_INTEN_PREGION0RA_Msk, ///< Interrupt on PREGION[0].RA event.
NRF_MWU_INT_PREGION1_WRITE_MASK = MWU_INTEN_PREGION1WA_Msk, ///< Interrupt on PREGION[1].WA event.
NRF_MWU_INT_PREGION1_READ_MASK = MWU_INTEN_PREGION1RA_Msk, ///< Interrupt on PREGION[1].RA event.
} nrf_mwu_int_mask_t;
/** @brief MWU region watch masks. */
typedef enum
{
NRF_MWU_WATCH_REGION0_WRITE = MWU_REGIONEN_RGN0WA_Msk, ///< Region 0 write access watch mask
NRF_MWU_WATCH_REGION0_READ = MWU_REGIONEN_RGN0RA_Msk, ///< Region 0 read access watch mask
NRF_MWU_WATCH_REGION1_WRITE = MWU_REGIONEN_RGN1WA_Msk, ///< Region 1 write access watch mask
NRF_MWU_WATCH_REGION1_READ = MWU_REGIONEN_RGN1RA_Msk, ///< Region 1 read access watch mask
NRF_MWU_WATCH_REGION2_WRITE = MWU_REGIONEN_RGN2WA_Msk, ///< Region 2 write access watch mask
NRF_MWU_WATCH_REGION2_READ = MWU_REGIONEN_RGN2RA_Msk, ///< Region 2 read access watch mask
NRF_MWU_WATCH_REGION3_WRITE = MWU_REGIONEN_RGN3WA_Msk, ///< Region 3 write access watch mask
NRF_MWU_WATCH_REGION3_READ = MWU_REGIONEN_RGN3RA_Msk, ///< Region 3 read access watch mask
NRF_MWU_WATCH_PREGION0_WRITE = MWU_REGIONEN_PRGN0WA_Msk, ///< Peripheral region 0 write access watch mask
NRF_MWU_WATCH_PREGION0_READ = MWU_REGIONEN_PRGN0RA_Msk, ///< Peripheral region 0 read access watch mask
NRF_MWU_WATCH_PREGION1_WRITE = MWU_REGIONEN_PRGN1WA_Msk, ///< Peripheral region 1 write access watch mask
NRF_MWU_WATCH_PREGION1_READ = MWU_REGIONEN_PRGN1RA_Msk, ///< Peripheral region 1 read access watch mask
} nrf_mwu_region_watch_t;
/**
* @brief Function for checking the state of a specific MWU event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mwu_event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg,
nrf_mwu_event_t mwu_event);
/**
* @brief Function for clearing a specific MWU event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mwu_event Event to clear.
*/
__STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg,
nrf_mwu_event_t mwu_event);
/**
* @brief Function for getting the address of a specific MWU event register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mwu_event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg,
nrf_mwu_event_t mwu_event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for retrieving the state of a specific interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mwu_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg,
nrf_mwu_int_mask_t mwu_int);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for enabling specified non-maskable interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for retrieving the state of a specific non-maskable interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mwu_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg,
nrf_mwu_int_mask_t mwu_int);
/**
* @brief Function for disabling specified non-maskable interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_mwu_nmi_disable(NRF_MWU_Type * p_reg, uint32_t int_mask);
/**
* @brief Function for setting address range of the specified user region.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] region_idx Region number to configure.
* @param[in] start_addr Memory address defining the beginning of the region.
* @param[in] end_addr Memory address defining the end of the region.
*/
__STATIC_INLINE void nrf_mwu_user_region_range_set(NRF_MWU_Type * p_reg,
uint8_t region_idx,
uint32_t start_addr,
uint32_t end_addr);
/**
* @brief Function for enabling memory access watch mechanism.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] reg_watch_mask Mask that defines regions and access types to watch.
* Compose this mask from @ref nrf_mwu_region_watch_t values.
*/
__STATIC_INLINE void nrf_mwu_region_watch_enable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask);
/**
* @brief Function for disabling memory access watch mechanism.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] reg_watch_mask Mask that defines regions and access types to stop watching.
* Compose this mask from @ref nrf_mwu_region_watch_t values.
*/
__STATIC_INLINE void nrf_mwu_region_watch_disable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask);
/**
* @brief Function for getting memory access watch configuration mask.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Mask that defines regions and access types being watched.
*/
__STATIC_INLINE uint32_t nrf_mwu_region_watch_get(NRF_MWU_Type const * p_reg);
/**
* @brief Function for configuring peripheral subregions for watching.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] per_reg_idx Peripheral region containing specified subregions.
* @param[in] subregion_mask Mask that defines subregions to include into the specified peripheral region.
*/
__STATIC_INLINE void nrf_mwu_subregions_configure(NRF_MWU_Type * p_reg,
uint8_t per_reg_idx,
uint32_t subregion_mask);
/**
* @brief Function for getting the mask of the write access flags of peripheral subregions
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] per_reg_idx Peripheral region containing subregions to check.
*
* @return Mask specifying subregions that were write accessed.
*/
__STATIC_INLINE uint32_t nrf_mwu_subregions_write_accesses_get(NRF_MWU_Type const * p_reg,
uint8_t per_reg_idx);
/**
* @brief Function for clearing write access flags of peripheral subregions.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] per_reg_idx Peripheral region containing subregion accesses to clear.
* @param[in] subregion_mask Mask that defines subregion write accesses to clear.
*/
__STATIC_INLINE void nrf_mwu_subregions_write_accesses_clear(NRF_MWU_Type * p_reg,
uint8_t per_reg_idx,
uint32_t subregion_mask);
/**
* @brief Function for getting the mask of the read access flags of peripheral subregions
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] per_reg_idx Peripheral region containing subregions to check.
*
* @return Mask specifying subregions that were read accessed.
*/
__STATIC_INLINE uint32_t nrf_mwu_subregions_read_accesses_get(NRF_MWU_Type const * p_reg,
uint8_t per_reg_idx);
/**
* @brief Function for clearing read access flags of peripheral subregions.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] per_reg_idx Peripheral region containing subregion accesses to clear.
* @param[in] subregion_mask Mask that defines subregion read accesses to clear.
*/
__STATIC_INLINE void nrf_mwu_subregions_read_accesses_clear(NRF_MWU_Type * p_reg,
uint8_t per_reg_idx,
uint32_t subregion_mask);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg,
nrf_mwu_event_t mwu_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event);
}
__STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg,
nrf_mwu_event_t mwu_event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event)) = 0;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event));
(void)dummy;
#endif
}
__STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg,
nrf_mwu_event_t mwu_event)
{
return (uint32_t)((uint8_t *)p_reg + (uint32_t)mwu_event);
}
__STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask)
{
p_reg->INTENSET = int_mask;
}
__STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg,
nrf_mwu_int_mask_t mwu_int)
{
return (bool)(p_reg->INTENSET & mwu_int);
}
__STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask)
{
p_reg->INTENCLR = int_mask;
}
__STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask)
{
p_reg->NMIENSET = int_mask;
}
__STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg,
nrf_mwu_int_mask_t mwu_int)
{
return (bool)(p_reg->NMIENSET & mwu_int);
}
__STATIC_INLINE void nrf_mwu_nmi_disable(NRF_MWU_Type * p_reg, uint32_t int_mask)
{
p_reg->NMIENCLR = int_mask;
}
__STATIC_INLINE void nrf_mwu_user_region_range_set(NRF_MWU_Type * p_reg,
uint8_t region_idx,
uint32_t start_addr,
uint32_t end_addr)
{
NRFX_ASSERT(region_idx < NRFX_ARRAY_SIZE(NRF_MWU->REGION));
NRFX_ASSERT(end_addr >= start_addr);
p_reg->REGION[region_idx].START = start_addr;
p_reg->REGION[region_idx].END = end_addr;
}
__STATIC_INLINE void nrf_mwu_region_watch_enable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask)
{
p_reg->REGIONENSET = reg_watch_mask;
}
__STATIC_INLINE void nrf_mwu_region_watch_disable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask)
{
p_reg->REGIONENCLR = reg_watch_mask;
}
__STATIC_INLINE uint32_t nrf_mwu_region_watch_get(NRF_MWU_Type const * p_reg)
{
return p_reg->REGIONENSET;
}
__STATIC_INLINE void nrf_mwu_subregions_configure(NRF_MWU_Type * p_reg,
uint8_t per_reg_idx,
uint32_t subregion_mask)
{
NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
p_reg->PREGION[per_reg_idx].SUBS = subregion_mask;
}
__STATIC_INLINE uint32_t nrf_mwu_subregions_write_accesses_get(NRF_MWU_Type const * p_reg,
uint8_t per_reg_idx)
{
NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
return p_reg->PERREGION[per_reg_idx].SUBSTATWA;
}
__STATIC_INLINE void nrf_mwu_subregions_write_accesses_clear(NRF_MWU_Type * p_reg,
uint8_t per_reg_idx,
uint32_t subregion_mask)
{
NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
p_reg->PERREGION[per_reg_idx].SUBSTATWA = subregion_mask;
}
__STATIC_INLINE uint32_t nrf_mwu_subregions_read_accesses_get(NRF_MWU_Type const * p_reg,
uint8_t per_reg_idx)
{
NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
return p_reg->PERREGION[per_reg_idx].SUBSTATRA;
}
__STATIC_INLINE void nrf_mwu_subregions_read_accesses_clear(NRF_MWU_Type * p_reg,
uint8_t per_reg_idx,
uint32_t subregion_mask)
{
NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
p_reg->PERREGION[per_reg_idx].SUBSTATRA = subregion_mask;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_MWU_H__

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/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
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/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2012 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_nvmc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2012 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_pdm.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_power.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_ppi.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_pwm.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

16
ext/hal/nordic/nrfx/hal/nrf_qdec.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -399,9 +399,23 @@ __STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void)
__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled)
{
#if defined(QDEC_PSEL_A_CONNECT_Pos)
NRF_QDEC->PSEL.A = psela;
#else
NRF_QDEC->PSELA = psela;
#endif
#if defined(QDEC_PSEL_B_CONNECT_Pos)
NRF_QDEC->PSEL.B = pselb;
#else
NRF_QDEC->PSELB = pselb;
#endif
#if defined(QDEC_PSEL_LED_CONNECT_Pos)
NRF_QDEC->PSEL.LED = pselled;
#else
NRF_QDEC->PSELLED = pselled;
#endif
}
__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task)

2
ext/hal/nordic/nrfx/hal/nrf_qspi.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_radio.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_regulators.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_rng.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
ext/hal/nordic/nrfx/hal/nrf_rtc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

39
ext/hal/nordic/nrfx/hal/nrf_saadc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -384,7 +384,7 @@ __STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf
* @param[in] pselp Positive input.
* @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode.
*/
__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
nrf_saadc_input_t pselp,
nrf_saadc_input_t pseln);
@ -394,7 +394,7 @@ __STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
* @param[in] channel Channel number.
* @param[in] pselp Positive input.
*/
__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel,
__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel,
nrf_saadc_input_t pselp);
/**
@ -522,6 +522,27 @@ __STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample)
*/
__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void);
/**
* @brief Function for enabling the continuous sampling.
*
* This function configures the SAADC internal timer to automatically take new samples at a fixed
* sample rate. Trigger the START task to begin continuous sampling. To stop the sampling, trigger
* the STOP task.
*
* @note The internal timer can only be used when a single input channel is enabled.
*
* @param[in] cc Capture and compare value. Sample rate is 16 MHz/cc. Valid CC range is
* from 80 to 2047.
*/
__STATIC_INLINE void nrf_saadc_continuous_mode_enable(uint16_t cc);
/**
* @brief Function for disabling the continuous sampling.
*
* New samples can still be acquired by manually triggering the SAMPLE task or by PPI.
*/
__STATIC_INLINE void nrf_saadc_continuous_mode_disable(void);
/**
* @brief Function for initializing the SAADC channel.
*
@ -729,6 +750,18 @@ __STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void)
return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE;
}
__STATIC_INLINE void nrf_saadc_continuous_mode_enable(uint16_t cc)
{
NRFX_ASSERT((cc >= 80) && (cc <= 2047));
NRF_SAADC->SAMPLERATE = (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos)
| ((uint32_t)cc << SAADC_SAMPLERATE_CC_Pos);
}
__STATIC_INLINE void nrf_saadc_continuous_mode_disable(void)
{
NRF_SAADC->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos;
}
__STATIC_INLINE void nrf_saadc_channel_init(uint8_t channel,
nrf_saadc_channel_config_t const * const config)
{

16
ext/hal/nordic/nrfx/hal/nrf_spi.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -296,9 +296,23 @@ __STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
uint32_t mosi_pin,
uint32_t miso_pin)
{
#if defined(SPI_PSEL_SCK_CONNECT_Pos)
p_reg->PSEL.SCK = sck_pin;
#else
p_reg->PSELSCK = sck_pin;
#endif
#if defined(SPI_PSEL_MOSI_CONNECT_Pos)
p_reg->PSEL.MOSI = mosi_pin;
#else
p_reg->PSELMOSI = mosi_pin;
#endif
#if defined(SPI_PSEL_MISO_CONNECT_Pos)
p_reg->PSEL.MISO = miso_pin;
#else
p_reg->PSELMISO = miso_pin;
#endif
}
__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data)

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