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drivers: timer: add support for LPTIM on STM32H5

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Added support for LPTIM1/2 for STM32H503 and
LPTIM1 to LPTIM6 for STM32H56x/STM32H57x devices

Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
This commit is contained in:
Adam Berlinger 2024-04-02 18:08:06 +02:00 • committed by Johan Hedberg
commit 91acd6c1e0
3 changed files with 69 additions and 0 deletions
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3
drivers/timer/stm32_lptim_timer.c
View file

@ -478,6 +478,7 @@ static int sys_clock_driver_init(void)
LL_LPTIM_SetPrescaler(LPTIM, (__CLZ(__RBIT(lptim_clock_presc)) << LPTIM_CFGR_PRESC_Pos)); LL_LPTIM_SetPrescaler(LPTIM, (__CLZ(__RBIT(lptim_clock_presc)) << LPTIM_CFGR_PRESC_Pos));
#if defined(CONFIG_SOC_SERIES_STM32U5X) || \ #if defined(CONFIG_SOC_SERIES_STM32U5X) || \
defined(CONFIG_SOC_SERIES_STM32H5X) || \
defined(CONFIG_SOC_SERIES_STM32WBAX) defined(CONFIG_SOC_SERIES_STM32WBAX)
LL_LPTIM_OC_SetPolarity(LPTIM, LL_LPTIM_CHANNEL_CH1, LL_LPTIM_OC_SetPolarity(LPTIM, LL_LPTIM_CHANNEL_CH1,
LL_LPTIM_OUTPUT_POLARITY_REGULAR); LL_LPTIM_OUTPUT_POLARITY_REGULAR);
@ -491,6 +492,7 @@ static int sys_clock_driver_init(void)
LL_LPTIM_TrigSw(LPTIM); LL_LPTIM_TrigSw(LPTIM);
#if defined(CONFIG_SOC_SERIES_STM32U5X) || \ #if defined(CONFIG_SOC_SERIES_STM32U5X) || \
defined(CONFIG_SOC_SERIES_STM32H5X) || \
defined(CONFIG_SOC_SERIES_STM32WBAX) defined(CONFIG_SOC_SERIES_STM32WBAX)
/* Enable the LPTIM before proceeding with configuration */ /* Enable the LPTIM before proceeding with configuration */
LL_LPTIM_Enable(LPTIM); LL_LPTIM_Enable(LPTIM);
@ -516,6 +518,7 @@ static int sys_clock_driver_init(void)
LL_LPTIM_ClearFlag_ARROK(LPTIM); LL_LPTIM_ClearFlag_ARROK(LPTIM);
#if !defined(CONFIG_SOC_SERIES_STM32U5X) && \ #if !defined(CONFIG_SOC_SERIES_STM32U5X) && \
!defined(CONFIG_SOC_SERIES_STM32H5X) && \
!defined(CONFIG_SOC_SERIES_STM32WBAX) !defined(CONFIG_SOC_SERIES_STM32WBAX)
/* Enable the LPTIM counter */ /* Enable the LPTIM counter */
LL_LPTIM_Enable(LPTIM); LL_LPTIM_Enable(LPTIM);

22
dts/arm/st/h5/stm32h5.dtsi
View file

@ -206,6 +206,28 @@
}; };
}; };
lptim1: timers@44004400 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x800>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x44004400 0x400>;
interrupts = <64 1>;
interrupt-names = "wakeup";
status = "disabled";
};
lptim2: timers@40009400 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x20>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40009400 0x400>;
interrupts = <70 1>;
interrupt-names = "wakeup";
status = "disabled";
};
usart1: serial@40013800 { usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>; reg = <0x40013800 0x400>;

44
dts/arm/st/h5/stm32h562.dtsi
View file

@ -54,6 +54,50 @@
}; };
}; };
lptim3: timers@44004800 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x44004800 0x400>;
interrupts = <127 1>;
interrupt-names = "wakeup";
status = "disabled";
};
lptim4: timers@44004C00 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x44004C00 0x400>;
interrupts = <128 1>;
interrupt-names = "wakeup";
status = "disabled";
};
lptim5: timers@44005000 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x44005000 0x400>;
interrupts = <129 1>;
interrupt-names = "wakeup";
status = "disabled";
};
lptim6: timers@44005400 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x8000>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x44005400 0x400>;
interrupts = <130 1>;
interrupt-names = "wakeup";
status = "disabled";
};
uart4: serial@40004c00 { uart4: serial@40004c00 {
compatible = "st,stm32-uart"; compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>; reg = <0x40004c00 0x400>;