soc: arm: ke1xf: add NXP Kinetis KE1xF SoC series support
Add initial support for the NXP Kinetis KE1xF SoC series (MKE14F16, MKE16F16, and MKE18F16). Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
Henrik Brix Andersen
Maureen Helm
parent
d4b9c0d600
commit
918579ebbf
25 changed files with 1150 additions and 0 deletions
278
soc/arm/nxp_kinetis/ke1xf/soc.c
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278
soc/arm/nxp_kinetis/ke1xf/soc.c
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/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* Based on NXP k6x soc.c, which is:
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <fsl_clock.h>
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#include <cortex_m/exc.h>
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/*
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* KE1xF flash configuration fields
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* These 16 bytes, which must be loaded to address 0x400, include default
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* protection, boot options and security settings.
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* They are loaded at reset to various Flash Memory module (FTFE) registers.
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*/
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u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
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/* Backdoor Comparison Key (unused) */
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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/* Program flash protection */
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0xFF, 0xFF, 0xFF, 0xFF,
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/*
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* Flash security: Backdoor key disabled, Mass erase enabled,
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* Factory access enabled, MCU is unsecure
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*/
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0xFE,
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/*
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* Flash nonvolatile option: Boot from ROM with BOOTCFG0/NMI
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* pin low, boot from flash with
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* BOOTCFG0/NMI pin high, RESET_b
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* pin dedicated, NMI enabled,
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* normal boot
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*/
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0x7d,
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/* EEPROM protection */
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0xFF,
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/* Data flash protection */
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0xFF,
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};
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#define ASSERT_WITHIN_RANGE(val, min, max, str) \
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BUILD_ASSERT_MSG(val >= min && val <= max, str)
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#define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \
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BUILD_ASSERT_MSG(val == 0 || val == 1 || val == 2 || val == 4 || \
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val == 8 || val == 16 || val == 2 || val == 64, str)
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#define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val)
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#define kSCG_AsyncClkDivBy0 kSCG_AsyncClkDisable
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#define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val)
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/* System Clock configuration */
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_SLOW, 2, 8,
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"Invalid SCG slow clock divider value");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_BUS, 1, 16,
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"Invalid SCG bus clock divider value");
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#if DT_NXP_KINETIS_SCG_0_CLK_SOURCE == KINETIS_SCG_SCLK_SRC_SPLL
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/* Core divider range is 1 to 4 with SPLL as clock source */
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_CORE, 1, 4,
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"Invalid SCG core clock divider value");
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#else
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_CORE, 1, 16,
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"Invalid SCG core clock divider value");
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#endif
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static const scg_sys_clk_config_t scg_sys_clk_config = {
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.divSlow = TO_SYS_CLK_DIV(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_SLOW),
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.divBus = TO_SYS_CLK_DIV(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_BUS),
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.divCore = TO_SYS_CLK_DIV(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_CORE),
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.src = DT_NXP_KINETIS_SCG_0_CLK_SOURCE
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};
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#ifdef DT_NXP_KINETIS_SCG_0_SOSC_FREQ
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/* System Oscillator (SOSC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_1,
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"Invalid SCG SOSC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_2,
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"Invalid SCG SOSC divider 2 value");
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static const scg_sosc_config_t scg_sosc_config = {
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.freq = DT_NXP_KINETIS_SCG_0_SOSC_FREQ,
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.monitorMode = kSCG_SysOscMonitorDisable,
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.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_2),
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.workMode = DT_NXP_KINETIS_SCG_0_SOSC_MODE
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};
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#endif /* DT_NXP_KINETIS_SCG_0_SOSC_FREQ */
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/* Slow Internal Reference Clock (SIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_1,
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"Invalid SCG SIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_2,
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"Invalid SCG SIRC divider 2 value");
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static const scg_sirc_config_t scg_sirc_config = {
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.enableMode = kSCG_SircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_2),
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#if MHZ(2) == DT_NXP_KINETIS_SCG_0_SIRC_RANGE
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.range = kSCG_SircRangeLow
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#elif MHZ(8) == DT_NXP_KINETIS_SCG_0_SIRC_RANGE
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.range = kSCG_SircRangeHigh
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#else
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#error Invalid SCG SIRC range
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#endif
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};
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/* Fast Internal Reference Clock (FIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_1,
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"Invalid SCG FIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_2,
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"Invalid SCG FIRC divider 2 value");
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static const scg_firc_config_t scg_firc_config = {
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.enableMode = kSCG_FircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_2),
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#if MHZ(48) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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.range = kSCG_FircRange48M,
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#elif MHZ(52) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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.range = kSCG_FircRange52M,
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#elif MHZ(56) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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.range = kSCG_FircRange56M,
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#elif MHZ(60) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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.range = kSCG_FircRange60M,
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#else
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#error Invalid SCG FIRC range
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#endif
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.trimConfig = NULL
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};
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/* System Phase-Locked Loop (SPLL) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_1,
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"Invalid SCG SPLL divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_2,
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"Invalid SCG SPLL divider 2 value");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_PRE, 1, 8,
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"Invalid SCG SPLL pre divider value");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_SPLL_MULTIPLIER, 16, 47,
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"Invalid SCG SPLL multiplier value");
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static const scg_spll_config_t scg_spll_config = {
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.enableMode = kSCG_SysPllEnable,
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.monitorMode = kSCG_SysPllMonitorDisable,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_2),
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#if DT_NXP_KINETIS_SCG_0_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_SOSC
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.src = kSCG_SysPllSrcSysOsc,
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#elif DT_NXP_KINETIS_SCG_0_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_FIRC
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.src = kSCG_SysPllSrcFirc,
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#else
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#error Invalid SCG SPLL source
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#endif
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.prediv = (DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_PRE - 1U),
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.mult = (DT_NXP_KINETIS_SCG_0_SPLL_MULTIPLIER - 16U)
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};
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static ALWAYS_INLINE void clk_init(void)
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{
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const scg_sys_clk_config_t scg_sys_clk_config_safe = {
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.divSlow = kSCG_SysClkDivBy4,
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.divBus = kSCG_SysClkDivBy1,
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.divCore = kSCG_SysClkDivBy1,
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.src = kSCG_SysClkSrcSirc
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};
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scg_sys_clk_config_t current;
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#ifdef DT_NXP_KINETIS_SCG_0_SOSC_FREQ
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/* Optionally initialize system oscillator */
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CLOCK_InitSysOsc(&scg_sosc_config);
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CLOCK_SetXtal0Freq(scg_sosc_config.freq);
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#endif
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/* Configure SIRC */
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CLOCK_InitSirc(&scg_sirc_config);
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/* Temporary switch to safe SIRC in order to configure FIRC */
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CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config_safe);
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do {
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CLOCK_GetCurSysClkConfig(¤t);
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} while (current.src != scg_sys_clk_config_safe.src);
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CLOCK_InitFirc(&scg_firc_config);
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/* Configure System PLL */
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CLOCK_InitSysPll(&scg_spll_config);
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/* Only RUN mode supported for now */
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CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config);
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do {
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CLOCK_GetCurSysClkConfig(¤t);
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} while (current.src != scg_sys_clk_config.src);
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#ifdef CONFIG_UART_MCUX_LPUART_0
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CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART_1
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CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFircAsync);
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART_2
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CLOCK_SetIpSrc(kCLOCK_Lpuart2, kCLOCK_IpSrcFircAsync);
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#endif
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#ifdef DT_NXP_KINETIS_SCG_0_CLKOUT_SOURCE
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CLOCK_SetClkOutSel(DT_NXP_KINETIS_SCG_0_CLKOUT_SOURCE);
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#endif
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}
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static int ke1xf_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int old_level; /* old interrupt lock level */
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#if !defined(CONFIG_ARM_MPU)
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u32_t temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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/* Disable interrupts */
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old_level = irq_lock();
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#if !defined(CONFIG_ARM_MPU)
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/*
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* Disable memory protection and clear slave port errors.
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* Note that the KE1xF does not implement the optional ARMv7-M memory
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* protection unit (MPU), specified by the architecture (PMSAv7), in the
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* Cortex-M4 core. Instead, the processor includes its own MPU module.
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*/
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temp_reg = SYSMPU->CESR;
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temp_reg &= ~SYSMPU_CESR_VLD_MASK;
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temp_reg |= SYSMPU_CESR_SPERR_MASK;
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SYSMPU->CESR = temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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z_clearfaults();
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/* Initialize system clocks and PLL */
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clk_init();
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/*
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* Install default handler that simply resets the CPU if
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* configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* Restore interrupt state */
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irq_unlock(old_level);
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return 0;
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}
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void _WdogInit(void)
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{
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/*
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* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!! Watchdog
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* reconfiguration must take place within 128 bus clocks from
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* unlocking. Single stepping through the code will cause the
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* watchdog to close the unlock window again.
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*/
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/* Unlock watchdog to enable reconfiguration after bootloader */
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WDOG->CNT = WDOG_UPDATE_KEY;
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while (!(WDOG->CS & WDOG_CS_ULK_MASK)) {
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;
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}
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/*
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* Watchdog reconfiguration only takes effect after writing to
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* both TOVAL and CS registers.
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*/
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WDOG->TOVAL = 1024;
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WDOG->CS = WDOG_CS_EN(0) | WDOG_CS_UPDATE(1);
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while (!(WDOG->CS & WDOG_CS_RCS_MASK)) {
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;
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}
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}
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SYS_INIT(ke1xf_init, PRE_KERNEL_1, 0);
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