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arm: Move bsp/CortexM to core/cortex_m

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Eliminates bsp directory as part of transforming BSPs to platforms.

Change-Id: I8b5366bf32797ddbb1bfa3520ddfeed6344cec2f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This commit is contained in:
Peter Mitsis 2015-07-24 14:07:03 -04:00 • committed by Anas Nashif
commit 916dcff7a8
14 changed files with 3 additions and 3 deletions
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2
arch/arm/core/Makefile
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@ -11,3 +11,5 @@ obj-y = atomic.o exc_exit.o ffs.o irq_init.o \
fatal.o sys_fatal_error_handler.o
obj-$(CONFIG_MICROKERNEL) += task_abort.o
obj-$(CONFIG_CPU_CORTEX_M) += cortex_m/

243
arch/arm/core/cortex_m/Kconfig Normal file
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@ -0,0 +1,243 @@
# Kconfig - ARM BSP CortexM configuration options
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1) Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2) Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# 3) Neither the name of Wind River Systems nor the names of its contributors
# may be used to endorse or promote products derived from this software without
# specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
menu "ARM Cortex CPU options"
config CPU_CORTEX
bool "ARM CORTEX"
default n
select ARM
help
This option signifies the use of a CPU of the Cortex family.
config CPU_CORTEX_M
bool "ARM Cortex-M"
default n
select CPU_CORTEX
select ISA_THUMB2
help
This option signifies the use of a CPU of the Cortex-M family.
config CPU_CORTEX_M3_M4
bool "ARM Cortex-M3 or ARM Cortex-M4"
default n
select CPU_CORTEX_M
help
This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
choice
prompt "ARM Cortex M3 or M4 Processor"
default CPU_CORTEX_M4
config CPU_CORTEX_M3
bool "ARM Cortex-M3"
select CPU_CORTEX_M3_M4
help
This option signifies the use of a Cortex-M3 CPU
config CPU_CORTEX_M4
bool "ARM Cortex-M4"
select CPU_CORTEX_M3_M4
help
This option signifies the use of a Cortex-M4 CPU
endchoice
endmenu
menu "ARM Cortex-M family options"
depends on CPU_CORTEX_M
config LDREX_STREX_AVAILABLE
bool
default y
config DATA_ENDIANNESS_LITTLE
bool
default y
help
This is driven by the processor implementation, since it is fixed in
hardware. The BSP should set this value to 'n' if the data is
implemented as big endian.
config STACK_ALIGN_DOUBLE_WORD
bool
prompt "Align stacks on double-words (8 octets)"
default y
help
This is needed to conform to AAPCS, the procedure call standard for
the ARM. It wastes stack space.
config STACK_GROWS_DOWN
bool
prompt "Stacks grow down"
default y
help
Stacks can grow either up or down. Down is the default. Don't change
this unless you have a very good reason to do so.
config NUM_IRQ_PRIO_BITS
int
#hidden option, implemented by BSP
help
Cortex-M chips can implement up to 8 bits of interrupt priorities,
for a maximum of 256 priorities. Most chips implement fewer than 8.
The BSP must define the correct value.
config RUNTIME_NMI
bool
prompt "Attach an NMI handler at runtime"
default n
help
The kernel provides a simple NMI handler that simply hangs in a tight
loop if triggered. This fills the requirement that there must be an
NMI handler installed when the CPU boots. If a custom handler is
needed, enable this option and attach it via _NmiHandlerSet().
config FAULT_DUMP
int
prompt "Fault dump level"
default 2
help
Different levels for display information when a fault occurs.
2: The default. Display specific and verbose information. Consumes
the most memory (long strings).
1: Display general and short information. Consumes less memory
(short strings).
0: Off.
config XIP
default y
endmenu
menu "ARM Cortex-M3/M4 options"
depends on CPU_CORTEX_M3_M4
config SW_ISR_TABLE
bool
prompt "Enable software interrupt handler table"
default y
help
Enable an interrupt handler table implemented in software. This
table, unlike ISRs connected directly in the vector table, allow
a parameter to be passed to the interrupt handlers. Also, invoking
the exeception/interrupt exit stub is automatically done.
This has to be enabled for dynamically connecting interrupt handlers
at runtime (SW_ISR_TABLE_DYNAMIC).
config SW_ISR_TABLE_DYNAMIC
bool
prompt "Allow installing interrupt handlers at runtime"
depends on SW_ISR_TABLE
default y
help
This option enables irq_connect(). It moves the ISR table to
SRAM so that it is writable. This has the side-effect of removing
write-protection on the ISR table.
config SW_ISR_TABLE_STATIC_CUSTOM
bool
prompt "Projects provide a custom static software ISR table"
depends on SW_ISR_TABLE && !SW_ISR_TABLE_DYNAMIC
default n
help
Projects, not the BSP, provide a software table of ISR and their
parameters. The table is static, and thus ISRs cannot be connected
at runtime.
config SW_ISR_TABLE_BSP
bool
# omit prompt to signify a "hidden" option
depends on SW_ISR_TABLE_DYNAMIC || (SW_ISR_TABLE && !SW_ISR_TABLE_STATIC_CUSTOM)
default y
help
Not user-selectable, helps build system logic.
config IRQ_VECTOR_TABLE_CUSTOM
bool
prompt "Projects provide a custom static IRQ part of vector table"
depends on !SW_ISR_TABLE
default n
help
Projects, not the BSP, provide the IRQ part of the vector table.
This is the table of interrupt handlers with the best potential
performance, but is the less flexible.
The ISRs are installed directly in the vector table, thus are
directly called by the CPU when an interrupt is taken. This adds
the least overhead when handling an interrupt.
Downsides:
- ISRs cannot have a parameter
- ISRs cannot be connected at runtime
- ISRs must notify the kernel manually by invoking _IntExit() when
then are about to return.
config IRQ_VECTOR_TABLE_BSP
bool
# omit prompt to signify a "hidden" option
depends on SW_ISR_TABLE || !IRQ_VECTOR_TABLE_CUSTOM
default y
help
Not user-selectable, helps build system logic.
config ZERO_LATENCY_IRQS
bool
prompt "Enable zero-latency interrupts"
default n
help
Interrupt locking is done by setting exception masking to priority
one, thus allowing exception of priority zero to still come in. By
default, the kernel verifies, via __ASSERT() statements, that the
interrupt priority is not set to zero when either connecting them or
setting their priority. Enabling this option disables the check,
thus allowing setting the priority of interrupts to zero.
Note that this is a somewhat dangerous option: ISRs of priority zero
interrupts cannot use any kernel functionality.
config ARCH_HAS_TASK_ABORT
bool
# omit prompt to signify a "hidden" option
default y
config ARCH_HAS_NANO_FIBER_ABORT
bool
# omit prompt to signify a "hidden" option
default y
endmenu

8
arch/arm/core/cortex_m/Makefile Normal file
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@ -0,0 +1,8 @@
ccflags-y +=-I$(srctree)/include/drivers
ccflags-y +=-I$(srctree)/arch/$(ARCH)/platforms/$(strip $(CONFIG_PLATFORM))
asflags-y = $(ccflags-y)
obj-y = vector_table.o reset.o \
prep_c.o scs.o scb.o nmi.o \
sw_isr_table.o

117
arch/arm/core/cortex_m/nmi.c Normal file
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/* nmi.c - NMI handler infrastructure */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Provides a boot time handler that simply hangs in a sleep loop, and a run time
handler that resets the CPU. Also provides a mechanism for hooking a custom
run time handler.
*/
#include <nanokernel.h>
#include <arch/cpu.h>
#include <misc/printk.h>
#include <toolchain.h>
#include <sections.h>
extern void _SysNmiOnReset(void);
#if !defined(CONFIG_RUNTIME_NMI)
#define handler _SysNmiOnReset
#endif
#ifdef CONFIG_RUNTIME_NMI
typedef void (*_NmiHandler_t)(void);
static _NmiHandler_t handler = _SysNmiOnReset;
/**
*
* @brief Default NMI handler installed when kernel is up
*
* The default handler outputs a error message and reboots the target. It is
* installed by calling _NmiInit();
*
* @return N/A
*/
static void _DefaultHandler(void)
{
printk("NMI received! Rebooting...\n");
_ScbSystemReset();
}
/**
*
* @brief Install default runtime NMI handler
*
* Meant to be called by BSP code if they want to install a simple NMI handler
* that reboots the target. It should be installed after the console is
* initialized.
*
* @return N/A
*/
void _NmiInit(void)
{
handler = _DefaultHandler;
}
/**
*
* @brief Install a custom runtime NMI handler
*
* Meant to be called by BSP code if they want to install a custom NMI handler
* that reboots. It should be installed after the console is initialized if it is
* meant to output to the console.
*
* @return N/A
*/
void _NmiHandlerSet(void (*pHandler)(void))
{
handler = pHandler;
}
#endif /* CONFIG_RUNTIME_NMI */
/**
*
* @brief Handler installed in the vector table
*
* Simply call what is installed in 'static void(*handler)(void)'.
*
* @return N/A
*/
void __nmi(void)
{
handler();
_ExcExit();
}

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arch/arm/core/cortex_m/prep_c.c Normal file
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/* prep_c.c - full C support initialization */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Initialization of full C support: zero the .bss, copy the .data if XIP,
call _Cstart().
Stack is available in this module, but not the global data/bss until their
initialization is performed.
*/
#include <stdint.h>
#include <toolchain.h>
#include <linker-defs.h>
/**
*
* @brief Clear BSS
*
* This routine clears the BSS region, so all bytes are 0.
*
* @return N/A
*/
static void bssZero(void)
{
volatile uint32_t *pBSS = (uint32_t *)&__bss_start;
unsigned int n;
for (n = 0; n < (unsigned int)&__bss_num_words; n++) {
pBSS[n] = 0;
}
}
/**
*
* @brief Copy the data section from ROM to RAM
*
* This routine copies the data section from ROM to RAM.
*
* @return N/A
*/
#ifdef CONFIG_XIP
static void dataCopy(void)
{
volatile uint32_t *pROM = (uint32_t *)&__data_rom_start;
volatile uint32_t *pRAM = (uint32_t *)&__data_ram_start;
unsigned int n;
for (n = 0; n < (unsigned int)&__data_num_words; n++) {
pRAM[n] = pROM[n];
}
}
#else
static void dataCopy(void)
{
}
#endif
extern FUNC_NORETURN void _Cstart(void);
/**
*
* @brief Prepare to and run C code
*
* This routine prepares for the execution of and runs C code.
*
* @return N/A
*/
void _PrepC(void)
{
bssZero();
dataCopy();
_Cstart();
CODE_UNREACHABLE;
}

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arch/arm/core/cortex_m/reset.S Normal file
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/* reset_s.S - reset handler */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Reset handler that prepares the system for running C code.
*/
#define _ASMLANGUAGE
#include <board.h>
#include <toolchain.h>
#include <sections.h>
#include <arch/cpu.h>
#include "vector_table.h"
_ASM_FILE_PROLOGUE
GTEXT(__reset)
/**
*
* @brief Reset vector
*
* Ran when the system comes out of reset. The processor is in thread mode with
* privileged level. At this point, the main stack pointer (MSP) is already
* pointing to a valid area in SRAM.
*
* Locking interrupts prevents anything but NMIs and hard faults from
* interrupting the CPU. A default NMI handler is already in place in the
* vector table, and the boot code should not generate hard fault, or we're in
* deep trouble.
*
* We want to use the process stack pointer (PSP) instead of the MSP, since the
* MSP is to be set up to point to the one-and-only interrupt stack during later
* boot. That would not be possible if in use for running C code.
*
* When these steps are completed, jump to _PrepC(), which will finish setting
* up the system for running C code.
*
* @return N/A
*/
SECTION_FUNC(TEXT,__reset)
/* lock interrupts: will get unlocked when switch to main task */
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
/*
* Set PSP and use it to boot without using MSP, so that it
* gets set to _interrupt_stack during nanoInit().
*/
ldr r0, =__CORTEXM_BOOT_PSP
msr PSP, r0
movs.n r0, #2 /* switch to using PSP (bit1 of CONTROL reg) */
msr CONTROL, r0
#ifdef CONFIG_WDOG_INIT
/* board-specific watchdog initialization is necessary */
bl _WdogInit
#endif
b _PrepC

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arch/arm/core/cortex_m/scb.c Normal file
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/* scb.h - ARM CORTEX-M3 System Control Block interface */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Most of the SCB interface consists of simple bit-flipping methods, and is
implemented as inline functions in scb.h. This module thus contains only data
definitions and more complex routines, if needed.
*/
#include <nanokernel.h>
#include <arch/cpu.h>
#include <misc/util.h>
#define SCB_AIRCR_VECTKEY_EN_W 0x05FA
/**
*
* @brief Reset the system
*
* This routine resets the processor.
*
* @return N/A
*/
void _ScbSystemReset(void)
{
union __aircr reg;
reg.val = __scs.scb.aircr.val;
reg.bit.vectkey = SCB_AIRCR_VECTKEY_EN_W;
reg.bit.sysresetreq = 1;
__scs.scb.aircr.val = reg.val;
}
/**
*
* @brief Set the number of priority groups based on the number
* of exception priorities desired
*
* Exception priorities can be divided in priority groups, inside which there is
* no preemption. The priorities inside a group are only used to decide which
* exception will run when more than one is ready to be handled.
*
* The number of priorities has to be a power of two, from 1 to 128.
*
* @return N/A
*/
void _ScbNumPriGroupSet(unsigned int n /* number of priorities */
)
{
unsigned int set;
union __aircr reg;
__ASSERT(_IsPowerOfTwo(n) && (n <= 128),
"invalid number of priorities");
set = find_first_set(n);
reg.val = __scs.scb.aircr.val;
/* num pri bit set prigroup
* ---------------------------------
* 1 1 7
* 2 2 6
* 4 3 5
* 8 4 4
* 16 5 3
* 32 6 2
* 64 7 1
* 128 8 0
*/
reg.bit.prigroup = 8 - set;
reg.bit.vectkey = SCB_AIRCR_VECTKEY_EN_W;
__scs.scb.aircr.val = reg.val;
}

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arch/arm/core/cortex_m/scs.c Normal file
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/* scs.c - ARM CORTEX-M Series System Control Space */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Most of the SCS interface consists of simple bit-flipping methods, and is
implemented as inline functions in scs.h. This module thus contains only data
definitions and more complex routines, if needed.
*/
#include <nanokernel.h>
#include <arch/cpu.h>
#include <toolchain.h>
#include <sections.h>
/* the linker always puts this object at 0xe000e000 */
volatile struct __scs __scs_section __scs;

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arch/arm/core/cortex_m/sw_isr_table.S Normal file
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/* ISR table for static ISR declarations for ARM */
/*
* Copyright (c) 2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Software ISR table for ARM
*/
#define _ASMLANGUAGE
#include <toolchain.h>
#include <sections.h>
#include <arch/cpu.h>
_ASM_FILE_PROLOGUE
/*
* enable proprocessor features, such
* as %expr - evaluate the expression and use it as a string
*/
.altmacro
/*
* Define an ISR table entry
* Define symbol as weak and give the section .gnu.linkonce
* prefix. This allows linker overload the symbol and the
* whole section by the one defined by a device driver
*/
.macro _isr_table_entry_declare index
WDATA(_isr_irq\index)
.section .gnu.linkonce.isr_irq\index
_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
.endm
/*
* Declare the ISR table
* Macro is recursive
*/
.macro _isr_table_declare from, to
_isr_table_entry_declare \from
.if \to-\from
_isr_table_declare %(\from + 1), \to
.endif
.endm
GTEXT(_irq_spurious)
GDATA(_sw_isr_table)
.section .isr_irq0
.align
_sw_isr_table:
_isr_table_declare 0 CONFIG_NUM_IRQS

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arch/arm/core/cortex_m/vector_table.S Normal file
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/* vector_table.S - populated vector table in ROM */
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Vector table in ROM for starting system. The reset vector is the system entry
point, ie. the first instruction executed.
The table is populated with all the system exception handlers. The NMI vector
must be populated with a valid handler since it can happen at any time. The
rest should not be triggered until the kernel is ready to handle them.
*/
#define _ASMLANGUAGE
#include <board.h>
#include <toolchain.h>
#include <sections.h>
#include <drivers/system_timer.h>
#include "vector_table.h"
_ASM_FILE_PROLOGUE
/* Diab requires a __start symbol */
SECTION_SUBSEC_FUNC(exc_vector_table,_Start,__start)
SECTION_SUBSEC_FUNC(exc_vector_table,_Start,_VectorTableROM)
.word __CORTEXM_BOOT_MSP
.word __reset
.word __nmi
.word __hard_fault
.word __mpu_fault
.word __bus_fault
.word __usage_fault
.word __reserved
.word __reserved
.word __reserved
.word __reserved
.word __svc
.word __debug_monitor
.word __reserved
.word __pendsv
.word _timer_int_handler

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arch/arm/core/cortex_m/vector_table.h Normal file
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/* vector_table.h - definitions for the boot vector table */
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Definitions for the boot vector table.
System exception handler names all have the same format:
__<exception name with underscores>
No other symbol has the same format, so they are easy to spot.
*/
#ifndef _VECTOR_TABLE__H_
#define _VECTOR_TABLE__H_
#ifdef _ASMLANGUAGE
#include <board.h>
#include <toolchain.h>
#include <sections.h>
/* location of MSP and PSP upon boot: at the end of SRAM */
.equ __CORTEXM_BOOT_MSP, (0x20000000 + SRAM_SIZE - 8)
.equ __CORTEXM_BOOT_PSP, (__CORTEXM_BOOT_MSP - 0x100)
GTEXT(__start)
GTEXT(_VectorTableROM)
GTEXT(__reset)
GTEXT(__nmi)
GTEXT(__hard_fault)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
GTEXT(__usage_fault)
GTEXT(__svc)
GTEXT(__debug_monitor)
GTEXT(__pendsv)
GTEXT(__reserved)
GTEXT(_PrepC)
GTEXT(_isr_wrapper)
#endif /* _ASMLANGUAGE */
#endif /* _VECTOR_TABLE__H_ */