aarch64: smccc: Decouple PSCI from SMCCC

The current code is assuming that the SMC/HVC helpers can only be used
by the PSCI driver. This is wrong because a mechanism to call into the
secure monitor should be made available regardless of using PSCI or not.

For example several SoCs relies on SMC calls to read/write e-fuses,
retrieve the chip ID, control power domains, etc...

This patch introduces a new CONFIG_HAS_ARM_SMCCC symbol to enable the
SMC/HVC helpers support and export that to drivers that require it.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2021-02-03 11:14:39 +01:00 committed by Anas Nashif
commit 90859c6bf3
4 changed files with 9 additions and 1 deletions

View file

@ -38,6 +38,12 @@ config ARM_CUSTOM_INTERRUPT_CONTROLLER
family cores. The Cortex-M family cores are always equipped with
the ARM Nested Vectored Interrupt Controller (NVIC).
config HAS_ARM_SMCCC
bool
help
Include support for the Secure Monitor Call (SMC) and Hypervisor
Call (HVC) instructions on Armv7 and above architectures.
if !ARM64
rsource "core/aarch32/Kconfig"
endif

View file

@ -22,7 +22,7 @@ zephyr_library_sources(
zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c)
zephyr_library_sources_ifdef(CONFIG_ARM_PSCI smccc-call.S)
zephyr_library_sources_ifdef(CONFIG_HAS_ARM_SMCCC smccc-call.S)
zephyr_library_sources_ifdef(CONFIG_AARCH64_IMAGE_HEADER header.S)
add_subdirectory_ifdef(CONFIG_ARM_MMU mmu)

View file

@ -9,6 +9,7 @@ config CPU_CORTEX_A
select HAS_FLASH_LOAD_OFFSET
select USE_SWITCH
select USE_SWITCH_SUPPORTED
select HAS_ARM_SMCCC
help
This option signifies the use of a CPU of the Cortex-A family.

View file

@ -6,6 +6,7 @@
config ARM_PSCI
bool "Support for the ARM Power State Coordination Interface (PSCI)"
depends on ARMV8_A
depends on HAS_ARM_SMCCC
help
Say Y here if you want Zephyr to communicate with system firmware
implementing the PSCI specification for CPU-centric power