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soc/riscv: correct the name of the register

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correct the name of bit5 of GCR2 register from SMB4E to SMB3E.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2021-01-07 09:32:31 +08:00 • committed by Anas Nashif
commit 8f4692083c
1 changed files with 1 additions and 1 deletions
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2
soc/riscv/riscv-ite/common/chip_chipregs.h
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@ -833,7 +833,7 @@
#define GCR2 ECREG(EC_REG_BASE_ADDR + 0x16F1)
#define CK32OE BIT(6)
#define SMB4E BIT(5)
#define SMB3E BIT(5)
#define PECIE BIT(4)
#define GCR3 ECREG(EC_REG_BASE_ADDR + 0x16F2)