dai: intel: dmic: nhlt: Move debug print code to a separate functions
Moved code fragments responsible for logging and verification of the configuration register values from the dai_dmic_set_config_nhlt function to a separate functions. Behavior of the code verifying the correctness of register values has been changed so that it only displays warnings. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit is contained in:
Adrian Warecki
Anas Nashif
parent
81944c5c62
commit
8ea53d49b6
1 changed files with 185 additions and 157 deletions
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@ -275,6 +275,180 @@ static inline int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const ui
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}
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#endif
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static int print_outcontrol(uint32_t val)
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{
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int bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8;
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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int bf9, bf10, bf11, bf12, bf13;
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#endif
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uint32_t ref;
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bf1 = FIELD_GET(OUTCONTROL_TIE, val);
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bf2 = FIELD_GET(OUTCONTROL_SIP, val);
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bf3 = FIELD_GET(OUTCONTROL_FINIT, val);
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bf4 = FIELD_GET(OUTCONTROL_FCI, val);
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bf5 = FIELD_GET(OUTCONTROL_BFTH, val);
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bf6 = FIELD_GET(OUTCONTROL_OF, val);
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bf7 = FIELD_GET(OUTCONTROL_IPM, val);
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bf8 = FIELD_GET(OUTCONTROL_TH, val);
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LOG_INF("OUTCONTROL = %08x", val);
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LOG_INF(" tie=%d, sip=%d, finit=%d, fci=%d", bf1, bf2, bf3, bf4);
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LOG_INF(" bfth=%d, of=%d, ipm=%d, th=%d", bf5, bf6, bf7, bf8);
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if (bf5 > OUTCONTROL_BFTH_MAX) {
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LOG_WRN("illegal BFTH value %d", bf5);
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return -EINVAL;
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}
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val);
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bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val);
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bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val);
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bf12 = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, val);
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bf13 = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, val);
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LOG_INF(" ipms1=%d, ipms2=%d, ipms3=%d, ipms4=%d", bf9, bf10, bf11, bf12);
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LOG_INF(" ipms_mode=%d", bf13);
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ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
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FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
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FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
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FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_1, bf9) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_2, bf10) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_3, bf11) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_4, bf12) | FIELD_PREP(OUTCONTROL_TH, bf8) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_MODE, bf13);
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#else
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ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
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FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
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FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
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FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_TH, bf8);
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#endif
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if (ref != val) {
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LOG_WRN("Some reserved bits are set in OUTCONTROL = 0x%08x", val);
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}
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return 0;
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}
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static void print_cic_control(uint32_t val)
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{
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int bf1, bf2, bf3, bf4, bf5, bf6, bf7;
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uint32_t ref;
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bf1 = FIELD_GET(CIC_CONTROL_SOFT_RESET, val);
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bf2 = FIELD_GET(CIC_CONTROL_CIC_START_B, val);
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bf3 = FIELD_GET(CIC_CONTROL_CIC_START_A, val);
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bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val);
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bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val);
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bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val);
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#ifndef CONFIG_SOC_SERIES_INTEL_ACE
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bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val);
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#else
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bf7 = -1;
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#endif
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LOG_DBG("CIC_CONTROL = %08x", val);
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LOG_DBG(" soft_reset=%d, cic_start_b=%d, cic_start_a=%d",
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bf1, bf2, bf3);
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LOG_DBG(" mic_b_polarity=%d, mic_a_polarity=%d, mic_mute=%d",
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bf4, bf5, bf6);
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ref = FIELD_PREP(CIC_CONTROL_SOFT_RESET, bf1) |
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FIELD_PREP(CIC_CONTROL_CIC_START_B, bf2) |
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FIELD_PREP(CIC_CONTROL_CIC_START_A, bf3) |
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FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) |
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FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) |
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FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6)
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#ifndef CONFIG_SOC_SERIES_INTEL_ACE
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| FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7)
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#endif
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;
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LOG_DBG(" stereo_mode=%d", bf7);
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if (ref != val) {
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LOG_WRN("Some reserved bits are set in CIC_CONTROL = 0x%08x", val);
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}
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}
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static void print_fir_control(uint32_t val)
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{
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int bf1, bf2, bf3, bf4, bf5, bf6;
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uint32_t ref;
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bf1 = FIELD_GET(FIR_CONTROL_START, val);
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bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
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#else
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bf3 = -1;
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#endif
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bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
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bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
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bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
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LOG_DBG("FIR_CONTROL = %08x", val);
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LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
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bf1, bf2, bf3);
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LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
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ref = FIELD_PREP(FIR_CONTROL_START, bf1) |
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FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) |
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) |
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#endif
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FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) |
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FIELD_PREP(FIR_CONTROL_MUTE, bf5) |
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FIELD_PREP(FIR_CONTROL_STEREO, bf6);
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if (ref != val) {
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LOG_WRN("Some reserved bits are set in FIR_CONTROL = 0x%08x", val);
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}
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}
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static void print_pdm_ctrl(const struct nhlt_pdm_ctrl_cfg *pdm_cfg)
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{
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int bf1, bf2, bf3, bf4, bf5;
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uint32_t val;
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LOG_DBG("CIC_CONTROL = %08x", pdm_cfg->cic_control);
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val = pdm_cfg->cic_config;
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bf1 = FIELD_GET(CIC_CONFIG_CIC_SHIFT, val);
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bf2 = FIELD_GET(CIC_CONFIG_COMB_COUNT, val);
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LOG_DBG("CIC_CONFIG = %08x", val);
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LOG_DBG(" cic_shift=%d, comb_count=%d", bf1, bf2);
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val = pdm_cfg->mic_control;
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#ifndef CONFIG_SOC_SERIES_INTEL_ACE
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bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val);
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#else
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bf1 = -1;
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#endif
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bf2 = FIELD_GET(MIC_CONTROL_CLK_EDGE, val);
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bf3 = FIELD_GET(MIC_CONTROL_PDM_EN_B, val);
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bf4 = FIELD_GET(MIC_CONTROL_PDM_EN_A, val);
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bf5 = FIELD_GET(MIC_CONTROL_PDM_CLKDIV, val);
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LOG_DBG("MIC_CONTROL = %08x", val);
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LOG_DBG(" clkdiv=%d, skew=%d, clk_edge=%d", bf5, bf1, bf2);
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LOG_DBG(" en_b=%d, en_a=%d", bf3, bf4);
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}
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static void print_fir_config(const struct nhlt_pdm_ctrl_fir_cfg *fir_cfg)
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{
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uint32_t val;
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int fir_decimation, fir_shift, fir_length;
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val = fir_cfg->fir_config;
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fir_length = FIELD_GET(FIR_CONFIG_FIR_LENGTH, val);
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fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
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fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
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LOG_DBG("FIR_CONFIG = %08x", val);
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LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
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fir_decimation, fir_shift, fir_length);
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print_fir_control(fir_cfg->fir_control);
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/* Use DC_OFFSET and GAIN as such */
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LOG_DBG("DC_OFFSET_LEFT = %08x", fir_cfg->dc_offset_left);
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LOG_DBG("DC_OFFSET_RIGHT = %08x", fir_cfg->dc_offset_right);
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LOG_DBG("OUT_GAIN_LEFT = %08x", fir_cfg->out_gain_left);
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LOG_DBG("OUT_GAIN_RIGHT = %08x", fir_cfg->out_gain_right);
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}
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int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cfg)
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{
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struct nhlt_pdm_ctrl_cfg *pdm_cfg[DMIC_HW_CONTROLLERS_MAX];
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@ -288,7 +462,6 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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uint32_t channel_ctrl_mask;
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uint32_t fir_control;
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uint32_t pdm_ctrl_mask;
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uint32_t ref = 0;
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uint32_t val;
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const uint8_t *p = bespoke_cfg;
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int num_fifos;
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@ -300,11 +473,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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int rate_div;
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int clk_div;
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int comb_count;
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int fir_decimation, fir_shift, fir_length;
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int bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8;
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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int bf9, bf10, bf11, bf12, bf13;
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#endif
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int fir_decimation, fir_length;
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int bfth;
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int ret;
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int p_mcic = 0;
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@ -347,48 +516,10 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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val = *(uint32_t *)p;
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out_control[n] = val;
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bf1 = FIELD_GET(OUTCONTROL_TIE, val);
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bf2 = FIELD_GET(OUTCONTROL_SIP, val);
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bf3 = FIELD_GET(OUTCONTROL_FINIT, val);
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bf4 = FIELD_GET(OUTCONTROL_FCI, val);
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bf5 = FIELD_GET(OUTCONTROL_BFTH, val);
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bf6 = FIELD_GET(OUTCONTROL_OF, val);
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bf7 = FIELD_GET(OUTCONTROL_IPM, val);
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bf8 = FIELD_GET(OUTCONTROL_TH, val);
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LOG_INF("dmic_set_config_nhlt(): OUTCONTROL%d = %08x", n, out_control[n]);
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LOG_INF(" tie=%d, sip=%d, finit=%d, fci=%d", bf1, bf2, bf3, bf4);
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LOG_INF(" bfth=%d, of=%d, ipm=%d, th=%d", bf5, bf6, bf7, bf8);
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if (bf5 > OUTCONTROL_BFTH_MAX) {
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LOG_ERR("dmic_set_config_nhlt(): illegal BFTH value");
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return -EINVAL;
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}
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val);
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bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val);
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bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val);
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bf12 = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, val);
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bf13 = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, val);
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LOG_INF(" ipms1=%d, ipms2=%d, ipms3=%d, ipms4=%d", bf9, bf10, bf11, bf12);
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LOG_INF(" ipms_mode=%d", bf13);
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ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
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FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
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FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
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FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_1, bf9) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_2, bf10) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_3, bf11) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_4, bf12) | FIELD_PREP(OUTCONTROL_TH, bf8) |
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FIELD_PREP(OUTCONTROL_IPM_SOURCE_MODE, bf13);
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#else
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ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
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FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
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FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
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FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_TH, bf8);
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#endif
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if (ref != val) {
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LOG_ERR("dmic_set_config_nhlt(): illegal OUTCONTROL%d = 0x%08x",
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n, val);
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return -EINVAL;
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ret = print_outcontrol(val);
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if (ret) {
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return ret;
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}
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p += sizeof(uint32_t);
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@ -446,67 +577,22 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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clk_div = FIELD_GET(MIC_CONTROL_PDM_CLKDIV, pdm_cfg[n]->mic_control);
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p_clkdiv = clk_div + 2;
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if (dai_dmic_global.active_fifos_mask == 0) {
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print_pdm_ctrl(pdm_cfg[n]);
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val = pdm_cfg[n]->cic_control;
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bf1 = FIELD_GET(CIC_CONTROL_SOFT_RESET, val);
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bf2 = FIELD_GET(CIC_CONTROL_CIC_START_B, val);
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bf3 = FIELD_GET(CIC_CONTROL_CIC_START_A, val);
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bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val);
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bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val);
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bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val);
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#ifndef CONFIG_SOC_SERIES_INTEL_ACE
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bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val);
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#else
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bf7 = -1;
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#endif
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LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val);
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LOG_DBG(" soft_reset=%d, cic_start_b=%d, cic_start_a=%d",
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bf1, bf2, bf3);
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LOG_DBG(" mic_b_polarity=%d, mic_a_polarity=%d, mic_mute=%d",
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bf4, bf5, bf6);
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ref = FIELD_PREP(CIC_CONTROL_SOFT_RESET, bf1) |
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FIELD_PREP(CIC_CONTROL_CIC_START_B, bf2) |
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FIELD_PREP(CIC_CONTROL_CIC_START_A, bf3) |
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FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) |
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FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) |
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FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6)
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#ifndef CONFIG_SOC_SERIES_INTEL_ACE
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| FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7)
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#endif
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;
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LOG_DBG(" stereo_mode=%d", bf7);
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if (ref != val) {
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LOG_WRN("dmic_set_config_nhlt(): illegal CIC_CONTROL = 0x%08x",
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val);
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}
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print_cic_control(val);
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/* Clear CIC_START_A and CIC_START_B */
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val = (val & ~(CIC_CONTROL_CIC_START_A | CIC_CONTROL_CIC_START_B));
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dai_dmic_write(dmic, base[n] + CIC_CONTROL, val);
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LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val);
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val = pdm_cfg[n]->cic_config;
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bf1 = FIELD_GET(CIC_CONFIG_CIC_SHIFT, val);
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LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val);
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LOG_DBG(" cic_shift=%d, comb_count=%d", bf1, comb_count);
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/* Use CIC_CONFIG as such */
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val = pdm_cfg[n]->cic_config;
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dai_dmic_write(dmic, base[n] + CIC_CONFIG, val);
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LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val);
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val = pdm_cfg[n]->mic_control;
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#ifndef CONFIG_SOC_SERIES_INTEL_ACE
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bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val);
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#else
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bf1 = -1;
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#endif
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bf2 = FIELD_GET(MIC_CONTROL_CLK_EDGE, val);
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bf3 = FIELD_GET(MIC_CONTROL_PDM_EN_B, val);
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bf4 = FIELD_GET(MIC_CONTROL_PDM_EN_A, val);
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LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
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LOG_DBG(" clkdiv=%d, skew=%d, clk_edge=%d", clk_div, bf1, bf2);
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LOG_DBG(" en_b=%d, en_a=%d", bf3, bf4);
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/* Clear PDM_EN_A and PDM_EN_B */
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val = pdm_cfg[n]->mic_control;
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val &= ~(MIC_CONTROL_PDM_EN_A | MIC_CONTROL_PDM_EN_B);
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dai_dmic_write(dmic, base[n] + MIC_CONTROL, val);
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LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
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@ -520,44 +606,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
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p_mfira = fir_decimation + 1;
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if (dmic->dai_config_params.dai_index == 0) {
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fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
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LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_A = %08x", val);
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LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
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fir_decimation, fir_shift, fir_length);
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print_fir_config(fir_cfg_a[n]);
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/* Use FIR_CONFIG_A as such */
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dai_dmic_write(dmic, base[n] + FIR_CONFIG_A, val);
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LOG_DBG("configure_registers(), FIR_CONFIG_A = %08x", val);
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val = fir_cfg_a[n]->fir_control;
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bf1 = FIELD_GET(FIR_CONTROL_START, val);
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bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
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#else
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bf3 = -1;
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#endif
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bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
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bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
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||||
bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
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LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", val);
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LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
|
||||
bf1, bf2, bf3);
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LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
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ref = FIELD_PREP(FIR_CONTROL_START, bf1) |
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||||
FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) |
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
|
||||
FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) |
|
||||
#endif
|
||||
FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) |
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||||
FIELD_PREP(FIR_CONTROL_MUTE, bf5) |
|
||||
FIELD_PREP(FIR_CONTROL_STEREO, bf6);
|
||||
|
||||
if (ref != val) {
|
||||
LOG_ERR("dmic_set_config_nhlt(): illegal FIR_CONTROL = 0x%08x",
|
||||
val);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Clear START, set MUTE */
|
||||
fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
|
||||
|
|
@ -567,19 +621,15 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
|
|||
/* Use DC_OFFSET and GAIN as such */
|
||||
val = fir_cfg_a[n]->dc_offset_left;
|
||||
dai_dmic_write(dmic, base[n] + DC_OFFSET_LEFT_A, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): DC_OFFSET_LEFT_A = %08x", val);
|
||||
|
||||
val = fir_cfg_a[n]->dc_offset_right;
|
||||
dai_dmic_write(dmic, base[n] + DC_OFFSET_RIGHT_A, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): DC_OFFSET_RIGHT_A = %08x", val);
|
||||
|
||||
val = fir_cfg_a[n]->out_gain_left;
|
||||
dai_dmic_write(dmic, base[n] + OUT_GAIN_LEFT_A, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): OUT_GAIN_LEFT_A = %08x", val);
|
||||
|
||||
val = fir_cfg_a[n]->out_gain_right;
|
||||
dai_dmic_write(dmic, base[n] + OUT_GAIN_RIGHT_A, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): OUT_GAIN_RIGHT_A = %08x", val);
|
||||
}
|
||||
|
||||
/* FIR B */
|
||||
|
|
@ -590,30 +640,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
|
|||
fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
|
||||
p_mfirb = fir_decimation + 1;
|
||||
if (dmic->dai_config_params.dai_index == 1) {
|
||||
fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_B = %08x", val);
|
||||
LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
|
||||
fir_decimation, fir_shift, fir_length);
|
||||
print_fir_config(fir_cfg_b[n]);
|
||||
|
||||
/* Use FIR_CONFIG_B as such */
|
||||
dai_dmic_write(dmic, base[n] + FIR_CONFIG_B, val);
|
||||
LOG_DBG("configure_registers(), FIR_CONFIG_B = %08x", val);
|
||||
|
||||
val = fir_cfg_b[n]->fir_control;
|
||||
bf1 = FIELD_GET(FIR_CONTROL_START, val);
|
||||
bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
|
||||
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
|
||||
bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
|
||||
#else
|
||||
bf3 = -1;
|
||||
#endif
|
||||
bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
|
||||
bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
|
||||
bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", val);
|
||||
LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
|
||||
bf1, bf2, bf3);
|
||||
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
|
||||
|
||||
/* Clear START, set MUTE */
|
||||
fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
|
||||
|
|
@ -623,19 +655,15 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
|
|||
/* Use DC_OFFSET and GAIN as such */
|
||||
val = fir_cfg_b[n]->dc_offset_left;
|
||||
dai_dmic_write(dmic, base[n] + DC_OFFSET_LEFT_B, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): DC_OFFSET_LEFT_B = %08x", val);
|
||||
|
||||
val = fir_cfg_b[n]->dc_offset_right;
|
||||
dai_dmic_write(dmic, base[n] + DC_OFFSET_RIGHT_B, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): DC_OFFSET_RIGHT_B = %08x", val);
|
||||
|
||||
val = fir_cfg_b[n]->out_gain_left;
|
||||
dai_dmic_write(dmic, base[n] + OUT_GAIN_LEFT_B, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): OUT_GAIN_LEFT_B = %08x", val);
|
||||
|
||||
val = fir_cfg_b[n]->out_gain_right;
|
||||
dai_dmic_write(dmic, base[n] + OUT_GAIN_RIGHT_B, val);
|
||||
LOG_DBG("dmic_set_config_nhlt(): OUT_GAIN_RIGHT_B = %08x", val);
|
||||
}
|
||||
|
||||
/* Set up FIR coefficients RAM */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue