From 8e5cf5fe8f80667abb25b70f35e878395bba86e9 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Thu, 23 Nov 2017 11:31:59 +0100 Subject: [PATCH] dts: stm32: Populate gpio nodes for stm32f0 series Introduce gpio nodes in stm32f0 dtsi files Signed-off-by: Erwan Gouriou --- dts/arm/st/stm32f0.dtsi | 45 +++++++++++++++++++++++++++++++++++++++ dts/arm/st/stm32f072.dtsi | 12 +++++++++++ dts/arm/st/stm32f091.dtsi | 12 +++++++++++ 3 files changed, 69 insertions(+) diff --git a/dts/arm/st/stm32f0.dtsi b/dts/arm/st/stm32f0.dtsi index 39becb394f5..a6d81087e48 100644 --- a/dts/arm/st/stm32f0.dtsi +++ b/dts/arm/st/stm32f0.dtsi @@ -60,6 +60,51 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x48000000 0x1800>; + + gpioa: gpio@48000000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00020000>; + label = "GPIOA"; + }; + + gpiob: gpio@48000400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>; + label = "GPIOB"; + }; + + gpioc: gpio@48000800 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00080000>; + label = "GPIOC"; + }; + + gpiod: gpio@48000c00 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00100000>; + label = "GPIOD"; + }; + + gpiof: gpio@48001400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00400000>; + label = "GPIOF"; + }; }; usart1: serial@40013800 { diff --git a/dts/arm/st/stm32f072.dtsi b/dts/arm/st/stm32f072.dtsi index e9ae46b531c..e3be4a9a073 100644 --- a/dts/arm/st/stm32f072.dtsi +++ b/dts/arm/st/stm32f072.dtsi @@ -8,6 +8,18 @@ / { soc { + pinctrl: pin-controller { + + gpioe: gpio@48001000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00200000>; + label = "GPIOE"; + }; + }; + spi2: spi@40003800 { compatible = "st,stm32-spi-fifo"; #address-cells = <1>; diff --git a/dts/arm/st/stm32f091.dtsi b/dts/arm/st/stm32f091.dtsi index 92292fc3265..12c40119d82 100644 --- a/dts/arm/st/stm32f091.dtsi +++ b/dts/arm/st/stm32f091.dtsi @@ -17,5 +17,17 @@ status = "disabled"; label = "SPI_2"; }; + + pinctrl: pin-controller { + + gpioe: gpio@48001000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00200000>; + label = "GPIOE"; + }; + }; }; };