From 8e5c95ed4b30afc26a821017e81a56c503c1dee7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Mon, 14 Apr 2025 09:31:24 +0200 Subject: [PATCH] drivers: dma: siwx91x: Allow static allocation of DMA channel descriptors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some instances of DMA (dma0) can use the normal sram to store their descriptors. In this case, it makes sense to allow the linker to allocate the memory rather than tweaking the memory layout. So, if the attribute silabs,sram-region is not defined, use a statically allocated buffer. Signed-off-by: Jérôme Pouiller --- drivers/dma/dma_silabs_siwx91x.c | 8 +++++++- dts/arm/silabs/siwg917.dtsi | 8 -------- dts/bindings/dma/silabs,siwx91x-dma.yaml | 7 ++++--- 3 files changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dma_silabs_siwx91x.c b/drivers/dma/dma_silabs_siwx91x.c index ba4f3c5dfb5..0fb61f010ff 100644 --- a/drivers/dma/dma_silabs_siwx91x.c +++ b/drivers/dma/dma_silabs_siwx91x.c @@ -649,6 +649,10 @@ static DEVICE_API(dma, siwx91x_dma_api) = { static UDMA_Channel_Info dma_channel_info_##inst[DT_INST_PROP(inst, dma_channels)]; \ SYS_MEM_BLOCKS_DEFINE_STATIC(desc_pool_##inst, sizeof(RSI_UDMA_DESC_T), \ CONFIG_DMA_SILABS_SIWX91X_SG_BUFFER_COUNT, 4); \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, silabs_sram_region), \ + (), \ + (static __aligned(512) RSI_UDMA_DESC_T \ + siwx91x_dma_chan_desc##inst[DT_INST_PROP(inst, dma_channels) * 2];)) \ static struct dma_siwx91x_channel_info \ zephyr_channel_info_##inst[DT_INST_PROP(inst, dma_channels)]; \ static struct dma_siwx91x_data dma_data_##inst = { \ @@ -670,7 +674,9 @@ static DEVICE_API(dma, siwx91x_dma_api) = { .clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \ .reg = (UDMA0_Type *)DT_INST_REG_ADDR(inst), \ .irq_number = DT_INST_PROP_BY_IDX(inst, interrupts, 0), \ - .sram_desc_addr = DT_REG_ADDR(DT_INST_PHANDLE(inst, silabs_sram_region)), \ + .sram_desc_addr = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, silabs_sram_region), \ + ((RSI_UDMA_DESC_T *)DT_REG_ADDR(DT_INST_PHANDLE(inst, silabs_sram_region))), \ + (siwx91x_dma_chan_desc##inst)), \ .irq_configure = siwx91x_dma_irq_configure_##inst, \ }; \ DEVICE_DT_INST_DEFINE(inst, &siwx91x_dma_init, NULL, &dma_data_##inst, &dma_cfg_##inst, \ diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index de037707c3c..5d7de0c83ce 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -32,13 +32,6 @@ reg = <0x00000000 DT_SIZE_K(191)>; }; - sram_dma0: memory-dma@2fc00 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x0002fc00 DT_SIZE_K(1)>; - zephyr,memory-region = "dma0"; - zephyr,memory-attr = ; - }; - sram_dma1: memory-dma@24061c00 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x24061c00 DT_SIZE_K(1)>; @@ -259,7 +252,6 @@ interrupts = <33 0>; interrupt-names = "dma0"; clocks = <&clock0 SIWX91X_CLK_DMA0>; - silabs,sram-region = <&sram_dma0>; #dma-cells = < 1>; dma-channels = <32>; status = "disabled"; diff --git a/dts/bindings/dma/silabs,siwx91x-dma.yaml b/dts/bindings/dma/silabs,siwx91x-dma.yaml index bdc0e3e0a3e..c6ff3b01da3 100644 --- a/dts/bindings/dma/silabs,siwx91x-dma.yaml +++ b/dts/bindings/dma/silabs,siwx91x-dma.yaml @@ -10,10 +10,11 @@ properties: silabs,sram-region: type: phandle - required: true description: | - SRAM Address for UDMA Descriptor Storage. This address must match to the - location used by the hardware. + SRAM Address for UDMA Descriptor Storage. Some instance require this + buffer to be placed in a specific area. If the instance doesn't have + this requirement, this attribute is not required and the memory will + will be automatically allocated. "#dma-cells": const: 1