michaelh/zephyr
1
0
Fork 0
Code Releases Activity

tests: drivers: stm32 clock control testing on stm32fx mcus

Browse source 
target is stm32fxx with clearing clock config
target is stm32fxx with pll from hsi clock config
target is stm32fxx with pll from hse clock config (with bypass)
target is stm32fxx with hse, hsi, clock config (no pll)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-03-02 16:51:11 +01:00 • committed by Maureen Helm
commit 8e0db1431e
12 changed files with 338 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

42
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/clear_f0_f1_f3_clocks.overlay Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32fxx.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-bypass;
/delete-property/ clock-frequency;
};
&clk_hsi {
status = "disabled";
};
&clk_lse {
status = "disabled";
};
&clk_lsi {
status = "disabled";
};
&pll {
/delete-property/ mul;
/delete-property/ div;
/delete-property/ prediv;
/delete-property/ xtpre;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
};

42
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/clear_f2_f4_f7_clocks.overlay Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32fxx.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-bypass;
/delete-property/ clock-frequency;
};
&clk_hsi {
status = "disabled";
};
&clk_lse {
status = "disabled";
};
&clk_lsi {
status = "disabled";
};
&pll {
/delete-property/ mul-n;
/delete-property/ div-m;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
};

28
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/f0_f3_pll_32_hse_8.overlay Normal file
View file

@ -0,0 +1,28 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
prediv = <4>;
mul = <16>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(32)>;
};

27
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/f0_f3_pll_32_hsi_8.overlay Normal file
View file

@ -0,0 +1,27 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
prediv = <2>;
mul = <8>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(32)>;
};

29
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/f1_pll_64_hse_8.overlay Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
xtpre;
mul = <16>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
/* apb1 prescaler is kept = 2 */
};

26
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/f1_pll_64_hsi_8.overlay Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll {
mul = <16>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
/* apb1 prescaler is kept = 2 */
};

30
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/f2_f4_f7_pll_64_hse_8.overlay Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <192>;
div-p = <6>;
div-q = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
};

28
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/f2_f4_f7_pll_64_hsi_16.overlay Normal file
View file

@ -0,0 +1,28 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <192>;
div-p = <6>;
div-q = <8>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
};

21
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hse_8_bypass.overlay Normal file
View file

@ -0,0 +1,21 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(8)>;
};

19
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hsi_8.overlay Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi { /* HSI RC: 8MHz, hsi_clk = 8MHz */
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
clock-frequency = <DT_FREQ_M(8)>;
};

12
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/src/test_stm32_clock_configuration.c
View file

@ -63,15 +63,24 @@ static void test_pll_src(void)
"Expected PLL src: HSE (%d). Actual PLL src: %d",
RCC_PLLSOURCE_HSE, pll_src);
#elif STM32_PLL_SRC_HSI
#if defined(CONFIG_SOC_SERIES_STM32F1X)
zassert_equal(RCC_PLLSOURCE_HSI_DIV2, pll_src,
"Expected PLL src: HSI (%d). Actual PLL src: %d",
RCC_PLLSOURCE_HSI_DIV2, pll_src);
#else
zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
"Expected PLL src: HSI (%d). Actual PLL src: %d",
RCC_PLLSOURCE_HSI, pll_src);
#endif /* CONFIG_SOC_SERIES_STM32F1X */
#elif STM32_PLL_SRC_MSI
zassert_equal(RCC_PLLSOURCE_MSI, pll_src,
"Expected PLL src: MSI (%d). Actual PLL src: %d",
RCC_PLLSOURCE_MSI, pll_src);
#else /* --> RCC_PLLSOURCE_NONE */
#if defined(CONFIG_SOC_SERIES_STM32L0X) || defined(CONFIG_SOC_SERIES_STM32L1X)
#if defined(CONFIG_SOC_SERIES_STM32L0X) || defined(CONFIG_SOC_SERIES_STM32L1X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F1X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || defined(CONFIG_SOC_SERIES_STM32F7X)
#define RCC_PLLSOURCE_NONE 0
/* check RCC_CR_PLLON bit to enable/disable the PLL, but no status function exist */
if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) {
@ -81,7 +90,6 @@ static void test_pll_src(void)
pll_src = RCC_PLLSOURCE_NONE;
}
#endif /* RCC_CR_PLLON */
zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
"Expected PLL src: none (%d). Actual PLL src: %d",
RCC_PLLSOURCE_NONE, pll_src);

36
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
View file

@ -82,3 +82,39 @@ tests:
drivers.stm32_clock_configuration.common.sysclksrc_msi_pll_48_msi_4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/pll_48_msi_4.overlay"
platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
drivers.stm32_clock_configuration.common.sysclksrc_f0_f3_hsi_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hsi_8.overlay"
platform_allow: nucleo_f091rc nucleo_f334r8
drivers.stm32_clock_configuration.common.sysclksrc_f0_f3_pll_32_hsi_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f0_f3_pll_32_hsi_8.overlay"
platform_allow: nucleo_f091rc nucleo_f334r8
drivers.stm32_clock_configuration.common.sysclksrc_f0_f3_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hse_8_bypass.overlay"
platform_allow: nucleo_f091rc nucleo_f334r8
drivers.stm32_clock_configuration.common.sysclksrc_f0_f3_pll_32_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f0_f3_pll_32_hse_8.overlay"
platform_allow: nucleo_f091rc nucleo_f334r8
drivers.stm32_clock_configuration.common.sysclksrc_f1_hsi_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_f103rb
drivers.stm32_clock_configuration.common.sysclksrc_f1_pll_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f1_pll_64_hsi_8.overlay"
platform_allow: nucleo_f103rb
drivers.stm32_clock_configuration.common.sysclksrc_f1_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hse_8.overlay"
platform_allow: nucleo_f103rb
drivers.stm32_clock_configuration.common.sysclksrc_f1_pll_64_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f1_pll_64_hse_8.overlay"
platform_allow: nucleo_f103rb
drivers.stm32_clock_configuration.common.sysclksrc_f2_f4_f7_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_f207zg nucleo_f411re nucleo_f429zi nucleo_f446re nucleo_f767zi
drivers.stm32_clock_configuration.common.sysclksrc_f2_f4_f7_pll_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/f2_f4_f7_pll_64_hsi_16.overlay"
platform_allow: nucleo_f207zg nucleo_f411re nucleo_f429zi nucleo_f446re nucleo_f767zi
drivers.stm32_clock_configuration.common.sysclksrc_f2_f4_f7_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/hse_8.overlay"
platform_allow: nucleo_f207zg nucleo_f411re nucleo_f429zi nucleo_f446re nucleo_f767zi
drivers.stm32_clock_configuration.common.sysclksrc_f2_f4_f7_pll_64_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/f2_f4_f7_pll_64_hse_8.overlay"
platform_allow: nucleo_f207zg nucleo_f411re nucleo_f429zi nucleo_f446re nucleo_f767zi