michaelh/zephyr
1
0
Fork 0
Code Releases Activity

board: pinctrl: board config for RT1060

Browse source 
enable pin control for RT1060 EVK.

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Hake Huang 2021-12-24 15:00:28 +08:00 • committed by David Leach
commit 8dda841e91
4 changed files with 64 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

53
boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi Normal file
View file

@ -0,0 +1,53 @@
/*
* Copyright (c) 2022, NXP
* SPDX-License-Identifier: Apache-2.0
*
* Generated by rt_cfg_utils.py on 2022-03-02
*/
#include <nxp/nxp_imx/rt/mimxrt1062-iomuxc.dtsi>
&pinctrl {
lpuart1_default: lpuart1_default {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx
&iomuxc_gpio_ad_b0_13_lpuart1_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
bias-disable;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
sai1_default: sai1_default {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_09_sai1_mclk
&iomuxc_gpio_ad_b1_13_sai1_tx_data00
&iomuxc_gpio_ad_b1_12_sai1_rx_data00
&iomuxc_gpio_ad_b1_14_sai1_tx_bclk
&iomuxc_gpio_ad_b1_15_sai1_tx_sync>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
};

10
boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts
View file

@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include <nxp/nxp_rt1060.dtsi> #include <nxp/nxp_rt1060.dtsi>
#include "mimxrt1060_evk-pinctrl.dtsi"
/ { / {
model = "NXP MIMXRT1060-EVK board"; model = "NXP MIMXRT1060-EVK board";
@ -175,6 +176,9 @@ arduino_serial: &lpuart3 {};
&lpuart1 { &lpuart1 {
status = "okay"; status = "okay";
current-speed = <115200>; current-speed = <115200>;
pinctrl-0 = <&lpuart1_default>;
pinctrl-1 = <&lpuart1_sleep>;
pinctrl-names = "default", "sleep";
}; };
&enet { &enet {
@ -229,6 +233,8 @@ zephyr_udc0: &usb1 {
&sai1 { &sai1 {
status = "okay"; status = "okay";
pinctrl-0 = <&sai1_default>;
pinctrl-names = "default";
}; };
/* Enable GPT for use as a hardware timer. This disables Cortex Systick. /* Enable GPT for use as a hardware timer. This disables Cortex Systick.
@ -237,3 +243,7 @@ zephyr_udc0: &usb1 {
&gpt_hw_timer { &gpt_hw_timer {
status = "okay"; status = "okay";
}; };
&iomuxcgpr {
status = "okay";
};

1
boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig
View file

@ -13,3 +13,4 @@ CONFIG_SERIAL=y
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_ARM_MPU=y CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y

30
boards/arm/mimxrt1060_evk/pinmux.c
View file

@ -114,22 +114,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0); IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
/* LPUART1 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL
/* LPUART3 TX/RX */ /* LPUART3 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
@ -400,20 +384,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6)); IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai1), okay) && CONFIG_I2S
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0x10B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u);
#endif
return 0; return 0;
} }