boards: 96b_neonkey: Use dts for clocks configuration
Convert board to use of device tree for clocks configuration. Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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2 changed files with 21 additions and 20 deletions
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@ -56,6 +56,26 @@
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};
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};
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};
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};
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&clk_hsi {
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status = "okay";
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};
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&pll {
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div-m = <16>;
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mul-n = <336>;
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div-p = <4>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(84)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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apb2-prescaler = <1>;
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};
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&usart1 {
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&usart1 {
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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current-speed = <115200>;
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current-speed = <115200>;
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@ -3,9 +3,6 @@
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CONFIG_SOC_SERIES_STM32F4X=y
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CONFIG_SOC_SERIES_STM32F4X=y
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CONFIG_SOC_STM32F411XE=y
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CONFIG_SOC_STM32F411XE=y
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# 84MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=84000000
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# Enable MPU
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# Enable MPU
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CONFIG_ARM_MPU=y
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CONFIG_ARM_MPU=y
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@ -21,25 +18,9 @@ CONFIG_PINMUX=y
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# enable GPIO
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# enable GPIO
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# clock configuration
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# Enable Clocks
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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# SYSCLK selection
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# PLL configuration
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CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
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# produce 84MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=16
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# APB1 clock must not exceed 50MHz limit
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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# console
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# console
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CONFIG_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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