driver: interrupt_controller: intc_clic: fixed access CLIC w/o privileged
Temporarily disabled PMP stack guard to allow access to CLIC M-mode register, because U-mode load/store (mstatus.MPRV=0x1,MPP=0x0) is restricted. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng
Benjamin Cabé
parent
9349d54074
commit
8dca182b14
1 changed files with 93 additions and 20 deletions
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@ -32,16 +32,95 @@ struct clic_config {
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mem_addr_t base;
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};
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struct pmp_stack_guard_key_t {
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unsigned long mstatus;
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unsigned int irq_key;
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};
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/*
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* M-mode CLIC memory-mapped registers are accessible only in M-mode.
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* Temporarily disable the PMP stack guard (set mstatus.MPRV = 0) to configure
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* CLIC registers, then restore the PMP stack guard using these functions.
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*/
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static ALWAYS_INLINE void disable_pmp_stack_guard(struct pmp_stack_guard_key_t *key)
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{
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if (IS_ENABLED(CONFIG_PMP_STACK_GUARD)) {
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key->irq_key = irq_lock();
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key->mstatus = csr_read_clear(mstatus, MSTATUS_MPRV);
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} else {
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ARG_UNUSED(key);
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}
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}
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static ALWAYS_INLINE void restore_pmp_stack_guard(struct pmp_stack_guard_key_t key)
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{
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if (IS_ENABLED(CONFIG_PMP_STACK_GUARD)) {
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csr_write(mstatus, key.mstatus);
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irq_unlock(key.irq_key);
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} else {
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ARG_UNUSED(key);
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}
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}
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static ALWAYS_INLINE void write_clic32(const struct device *dev, uint32_t offset, uint32_t value)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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disable_pmp_stack_guard(&key);
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sys_write32(value, reg_addr);
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restore_pmp_stack_guard(key);
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}
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static ALWAYS_INLINE uint32_t read_clic32(const struct device *dev, uint32_t offset)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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uint32_t reg;
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disable_pmp_stack_guard(&key);
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reg = sys_read32(reg_addr);
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restore_pmp_stack_guard(key);
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return reg;
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}
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static ALWAYS_INLINE void write_clic8(const struct device *dev, uint32_t offset, uint8_t value)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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disable_pmp_stack_guard(&key);
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sys_write8(value, reg_addr);
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restore_pmp_stack_guard(key);
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}
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static ALWAYS_INLINE uint8_t read_clic8(const struct device *dev, uint32_t offset)
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{
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const struct clic_config *config = dev->config;
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mem_addr_t reg_addr = config->base + offset;
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struct pmp_stack_guard_key_t key;
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uint32_t reg;
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disable_pmp_stack_guard(&key);
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reg = sys_read8(reg_addr);
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restore_pmp_stack_guard(key);
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return reg;
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}
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/**
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* @brief Enable interrupt
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*/
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void riscv_clic_irq_enable(uint32_t irq)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct clic_config *config = dev->config;
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union CLICINTIE clicintie = {.b = {.IE = 0x1}};
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sys_write8(clicintie.w, config->base + CLIC_INTIE(irq));
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write_clic8(dev, CLIC_INTIE(irq), clicintie.w);
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}
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/**
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@ -50,10 +129,9 @@ void riscv_clic_irq_enable(uint32_t irq)
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void riscv_clic_irq_disable(uint32_t irq)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct clic_config *config = dev->config;
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union CLICINTIE clicintie = {.b = {.IE = 0x0}};
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sys_write8(clicintie.w, config->base + CLIC_INTIE(irq));
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write_clic8(dev, CLIC_INTIE(irq), clicintie.w);
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}
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/**
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@ -62,8 +140,7 @@ void riscv_clic_irq_disable(uint32_t irq)
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int riscv_clic_irq_is_enabled(uint32_t irq)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct clic_config *config = dev->config;
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union CLICINTIE clicintie = {.w = sys_read8(config->base + CLIC_INTIE(irq))};
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union CLICINTIE clicintie = {.w = read_clic8(dev, CLIC_INTIE(irq))};
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return clicintie.b.IE;
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}
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@ -74,7 +151,6 @@ int riscv_clic_irq_is_enabled(uint32_t irq)
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void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct clic_config *config = dev->config;
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const struct clic_data *data = dev->data;
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/*
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@ -96,12 +172,12 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
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(MIN(pri, max_level) << (8U - data->nlbits)) |
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BIT_MASK(8U - data->intctlbits);
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sys_write8(intctrl, config->base + CLIC_INTCTRL(irq));
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write_clic8(dev, CLIC_INTCTRL(irq), intctrl);
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/* Set the IRQ operates in machine mode, non-vectoring and the trigger type. */
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union CLICINTATTR clicattr = {.b = {.mode = 0x3, .shv = 0x0, .trg = flags & BIT_MASK(3)}};
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sys_write8(clicattr.w, config->base + CLIC_INTATTR(irq));
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write_clic8(dev, CLIC_INTATTR(irq), clicattr.w);
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}
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/**
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@ -110,12 +186,11 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
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void riscv_clic_irq_vector_set(uint32_t irq)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct clic_config *config = dev->config;
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union CLICINTATTR clicattr = {.w = sys_read8(config->base + CLIC_INTATTR(irq))};
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union CLICINTATTR clicattr = {.w = read_clic8(dev, CLIC_INTATTR(irq))};
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/* Set Selective Hardware Vectoring. */
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clicattr.b.shv = 1;
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sys_write8(clicattr.w, config->base + CLIC_INTATTR(irq));
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write_clic8(dev, CLIC_INTATTR(irq), clicattr.w);
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}
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/**
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@ -124,25 +199,23 @@ void riscv_clic_irq_vector_set(uint32_t irq)
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void riscv_clic_irq_set_pending(uint32_t irq)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct clic_config *config = dev->config;
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union CLICINTIP clicintip = {.b = {.IP = 0x1}};
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sys_write8(clicintip.w, config->base + CLIC_INTIP(irq));
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write_clic8(dev, CLIC_INTIP(irq), clicintip.w);
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}
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static int clic_init(const struct device *dev)
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{
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const struct clic_config *config = dev->config;
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struct clic_data *data = dev->data;
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if (IS_ENABLED(CONFIG_NUCLEI_ECLIC)) {
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/* Configure the interrupt level threshold. */
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union CLICMTH clicmth = {.b = {.mth = 0x0}};
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sys_write32(clicmth.qw, config->base + CLIC_MTH);
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write_clic32(dev, CLIC_MTH, clicmth.qw);
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/* Detect the number of bits for the clicintctl register. */
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union CLICINFO clicinfo = {.qw = sys_read32(config->base + CLIC_INFO)};
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union CLICINFO clicinfo = {.qw = read_clic32(dev, CLIC_INFO)};
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data->intctlbits = clicinfo.b.intctlbits;
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@ -151,10 +224,10 @@ static int clic_init(const struct device *dev)
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}
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/* Configure the number of bits assigned to interrupt levels. */
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union CLICCFG cliccfg = {.qw = sys_read32(config->base + CLIC_CFG)};
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union CLICCFG cliccfg = {.qw = read_clic32(dev, CLIC_CFG)};
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cliccfg.w.nlbits = data->nlbits;
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sys_write32(cliccfg.qw, config->base + CLIC_CFG);
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write_clic32(dev, CLIC_CFG, cliccfg.qw);
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} else {
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/* Configure the interrupt level threshold by CSR mintthresh. */
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csr_write(CSR_MINTTHRESH, 0x0);
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@ -162,7 +235,7 @@ static int clic_init(const struct device *dev)
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/* Reset all interrupt control register */
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for (int i = 0; i < CONFIG_NUM_IRQS; i++) {
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sys_write32(0, config->base + CLIC_CTRL(i));
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write_clic32(dev, CLIC_CTRL(i), 0);
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}
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return 0;
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